f2407adc2.asm

TI的digital motor control lib的源代码。了解TI的编程规范

                AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
                                ; ARP = AR2. AR2 -> c2_out.
                                ; AR3 -> c2_gain
;--------------------------------------------------------------------------               
                SACL    *,AR3   ; Accumulator = c2_out
                                ; ARP = AR3. AR2-> c2_out.
                                ; AR3 -> c2_gain
;--------------------------------------------------------------------------
                LT      *+,AR2  ; c2_gain in Q13 TREG -> c2_gain
                                ; ARP = AR2. AR2 -> c2_out.  
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------
                MPY     *       ; PREG = c2_gain *c2_out (Q13 x Q15 = Q28)
                                ; ARP = AR2. AR2 -> c2_out.  
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------
                PAC             ; Accumulator = c2_gain *c2_out
                                ; ARP = AR2. AR2 -> c2_out.  
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------
                SACH    *+,3    ; Convert final result to Q15 
                                ; ARP = AR2. AR2 -> c3_out.  
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------            
       ;Read 3rd converted value
               
                LDP     #ADCL_CNTL1 >>7
                LACC    ADC_RESULT2
                                ; Load Accumulator with ADC_RESULT2 status 
                                ; ARP = AR2. AR2 -> c3_out.  
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------                                
                SFR             ; Right shift Accumulator 
                                ; contents by one bit
                                ; ARP = AR2. AR2 -> c3_out.
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------                                
                AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
                                ; ARP = AR2. AR2 -> c3_out. 
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------               
                SACL    *,AR3   ; Accumulator = c3_out
                                ; ARP = AR3. AR2 -> c3_out.
                                ; AR3 -> c3_gain
;--------------------------------------------------------------------------
                LT      *+,AR2  ; c3_gain in Q13 T->c3_gain
                                ; ARP = AR2. AR2 -> c3_out.
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------
                MPY     *       ; PREG = c3_gain *c3_out (Q13 x Q15 = Q28)
                                ; ARP = AR2. AR2 -> c3_out.
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------
                PAC             ; Accumulator = c1_gain *c1_out
                                ; ARP = AR2. AR2 -> c3_out.
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------
                SACH    *+,3    ; Convert final result to Q15 
                                ; ARP = AR2. AR2 -> c4_out.  
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------            
       ;Read 4th converted value
                  
                LDP     #ADCL_CNTL1 >>7
                LACC    ADC_RESULT3
                                ; Load Accumulator with ADC_RESULT3 status  
                                ; ARP = AR2. AR2 -> c4_out.  
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------                                
                SFR             ; Right shift Accumulator 
                                ; contents by one bit
                                ; ARP = AR2. AR2 -> c4_out. 
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------                                
                AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
                                ; ARP = AR2. AR2 -> c4_out.  
                                ; AR3 -> c4_gain
;--------------------------------------------------------------------------               
                SACL    *,AR3   ; Accumulator = c4_out
                                ; ARP = AR3. AR2 -> c4_out.  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------
                LT      *,AR2   ; c4_gain in Q13 
                                ; ARP = AR2. AR2 -> c4_out.  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------
                MPY     *       ; PREG = c4_gain *c4_out (Q13 x Q15 = Q28)
                                ; ARP = AR2. AR2 -> c4_out.  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------
                PAC             ; Accumulator = c4_gain *c4_out
                                ; ARP = AR2. AR2 -> c4_out.   
                                ; AR3->c4_gain
;--------------------------------------------------------------------------
                SACH    *+,3    ; Convert final result to Q15 
                                ; ARP = AR2. AR2->a4_ch_sel  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------            
    ;Start another conversion

F2407_ADC_Start_Next:

                LACC    *       ; Accumulator = a4_ch_sel
                                ; ARP = AR2. AR2->a4_ch_sel  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------                
                LDP     #ADCL_CNTL1 >>7
                SACL    CHSELSEQ1
                                ; CHSELSEQ1 = (a4_ch_sel*2) & (0x000E) 
                                ; ARP = AR2. AR2->a4_ch_sel  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------            
                SPLK    #0110000000000000b,ADCL_CNTL2 
                                ; Reset + SOC SEQ1
                                ; ARP = AR2. AR2->a4_ch_sel  
                                ; AR3->c4_gain
;--------------------------------------------------------------------------            
  
                          
__f2407_adc_update_exit:
                
    MAR     * ,AR1              ; set ARP = SP before you exit.
    SBRK    #(__F2407_ADC_Update_framesize+1)
                                ; deallocate frame, point to saved FP
    LAR     AR0, *-             ; restore frame pointer
    PSHD    *                   ; push return address on hardware stack
                   
    RET
                   
    .end