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📄 f2407adc2.lst

📁 TI的digital motor control lib的源代码。了解TI的编程规范
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     144                                            ; ARP = AR2. AR2 -> c2_out. 
     145                                            ; AR3 -> c2_gain
     146            ;--------------------------------------------------------------------------                                
     147 0017 be0a                  SFR             ; Right shift Accumulator 
     148                                            ; contents by one bit
     149                                            ; ARP = AR2. AR2 -> c2_out. 
     150                                            ; AR3 -> c2_gain
     151            ;--------------------------------------------------------------------------                                
     152 0018 bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         0019 7fff  
     153                                            ; ARP = AR2. AR2 -> c2_out.
     154                                            ; AR3 -> c2_gain
     155            ;--------------------------------------------------------------------------               
     156 001a 908b                  SACL    *,AR3   ; Accumulator = c2_out
     157                                            ; ARP = AR3. AR2-> c2_out.
     158                                            ; AR3 -> c2_gain
     159            ;--------------------------------------------------------------------------
     160 001b 73aa                  LT      *+,AR2  ; c2_gain in Q13 TREG -> c2_gain
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:12 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f2407adc2.asm                                                        PAGE    4

     161                                            ; ARP = AR2. AR2 -> c2_out.  
     162                                            ; AR3 -> c3_gain
     163            ;--------------------------------------------------------------------------
     164 001c 5480                  MPY     *       ; PREG = c2_gain *c2_out (Q13 x Q15 = Q28)
     165                                            ; ARP = AR2. AR2 -> c2_out.  
     166                                            ; AR3 -> c3_gain
     167            ;--------------------------------------------------------------------------
     168 001d be03                  PAC             ; Accumulator = c2_gain *c2_out
     169                                            ; ARP = AR2. AR2 -> c2_out.  
     170                                            ; AR3 -> c3_gain
     171            ;--------------------------------------------------------------------------
     172 001e 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     173                                            ; ARP = AR2. AR2 -> c3_out.  
     174                                            ; AR3 -> c3_gain
     175            ;--------------------------------------------------------------------------            
     176                   ;Read 3rd converted value
     177                           
     178 001f bce1                  LDP     #ADCL_CNTL1 >>7
     179 0020 102a                  LACC    ADC_RESULT2
     180                                            ; Load Accumulator with ADC_RESULT2 status 
     181                                            ; ARP = AR2. AR2 -> c3_out.  
     182                                            ; AR3 -> c3_gain
     183            ;--------------------------------------------------------------------------                                
     184 0021 be0a                  SFR             ; Right shift Accumulator 
     185                                            ; contents by one bit
     186                                            ; ARP = AR2. AR2 -> c3_out.
     187                                            ; AR3 -> c3_gain
     188            ;--------------------------------------------------------------------------                                
     189 0022 bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         0023 7fff  
     190                                            ; ARP = AR2. AR2 -> c3_out. 
     191                                            ; AR3 -> c3_gain
     192            ;--------------------------------------------------------------------------               
     193 0024 908b                  SACL    *,AR3   ; Accumulator = c3_out
     194                                            ; ARP = AR3. AR2 -> c3_out.
     195                                            ; AR3 -> c3_gain
     196            ;--------------------------------------------------------------------------
     197 0025 73aa                  LT      *+,AR2  ; c3_gain in Q13 T->c3_gain
     198                                            ; ARP = AR2. AR2 -> c3_out.
     199                                            ; AR3 -> c4_gain
     200            ;--------------------------------------------------------------------------
     201 0026 5480                  MPY     *       ; PREG = c3_gain *c3_out (Q13 x Q15 = Q28)
     202                                            ; ARP = AR2. AR2 -> c3_out.
     203                                            ; AR3 -> c4_gain
     204            ;--------------------------------------------------------------------------
     205 0027 be03                  PAC             ; Accumulator = c1_gain *c1_out
     206                                            ; ARP = AR2. AR2 -> c3_out.
     207                                            ; AR3 -> c4_gain
     208            ;--------------------------------------------------------------------------
     209 0028 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     210                                            ; ARP = AR2. AR2 -> c4_out.  
     211                                            ; AR3 -> c4_gain
     212            ;--------------------------------------------------------------------------            
     213                   ;Read 4th converted value
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:12 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f2407adc2.asm                                                        PAGE    5

     214                              
     215 0029 bce1                  LDP     #ADCL_CNTL1 >>7
     216 002a 102b                  LACC    ADC_RESULT3
     217                                            ; Load Accumulator with ADC_RESULT3 status  
     218                                            ; ARP = AR2. AR2 -> c4_out.  
     219                                            ; AR3 -> c4_gain
     220            ;--------------------------------------------------------------------------                                
     221 002b be0a                  SFR             ; Right shift Accumulator 
     222                                            ; contents by one bit
     223                                            ; ARP = AR2. AR2 -> c4_out. 
     224                                            ; AR3 -> c4_gain
     225            ;--------------------------------------------------------------------------                                
     226 002c bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         002d 7fff  
     227                                            ; ARP = AR2. AR2 -> c4_out.  
     228                                            ; AR3 -> c4_gain
     229            ;--------------------------------------------------------------------------               
     230 002e 908b                  SACL    *,AR3   ; Accumulator = c4_out
     231                                            ; ARP = AR3. AR2 -> c4_out.  
     232                                            ; AR3->c4_gain
     233            ;--------------------------------------------------------------------------
     234 002f 738a                  LT      *,AR2   ; c4_gain in Q13 
     235                                            ; ARP = AR2. AR2 -> c4_out.  
     236                                            ; AR3->c4_gain
     237            ;--------------------------------------------------------------------------
     238 0030 5480                  MPY     *       ; PREG = c4_gain *c4_out (Q13 x Q15 = Q28)
     239                                            ; ARP = AR2. AR2 -> c4_out.  
     240                                            ; AR3->c4_gain
     241            ;--------------------------------------------------------------------------
     242 0031 be03                  PAC             ; Accumulator = c4_gain *c4_out
     243                                            ; ARP = AR2. AR2 -> c4_out.   
     244                                            ; AR3->c4_gain
     245            ;--------------------------------------------------------------------------
     246 0032 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     247                                            ; ARP = AR2. AR2->a4_ch_sel  
     248                                            ; AR3->c4_gain
     249            ;--------------------------------------------------------------------------            
     250                ;Start another conversion
     251            
     252 0033       F2407_ADC_Start_Next:
     253            
     254 0033 1080                  LACC    *       ; Accumulator = a4_ch_sel
     255                                            ; ARP = AR2. AR2->a4_ch_sel  
     256                                            ; AR3->c4_gain
     257            ;--------------------------------------------------------------------------                
     258 0034 bce1                  LDP     #ADCL_CNTL1 >>7
     259 0035 9023                  SACL    CHSELSEQ1
     260                                            ; CHSELSEQ1 = (a4_ch_sel*2) & (0x000E) 
     261                                            ; ARP = AR2. AR2->a4_ch_sel  
     262                                            ; AR3->c4_gain
     263            ;--------------------------------------------------------------------------            
     264 0036 ae21                  SPLK    #0110000000000000b,ADCL_CNTL2 
         0037 6000  
     265                                            ; Reset + SOC SEQ1
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:12 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f2407adc2.asm                                                        PAGE    6

     266                                            ; ARP = AR2. AR2->a4_ch_sel  
     267                                            ; AR3->c4_gain
     268            ;--------------------------------------------------------------------------            
     269              
     270                                      
     271 0038       __f2407_adc_update_exit:
     272                            
     273 0038 8b89      MAR     * ,AR1              ; set ARP = SP before you exit.
     274 0039 7c02      SBRK    #(__F2407_ADC_Update_framesize+1)
     275                                            ; deallocate frame, point to saved FP
     276 003a 0090      LAR     AR0, *-             ; restore frame pointer
     277 003b 7680      PSHD    *                   ; push return address on hardware stack
     278                               
     279 003c ef00      RET
     280                               
     281                .end

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