f243adc2.lst

TI的digital motor control lib的源代码。了解TI的编程规范

TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:44 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f243adc2.asm                                                         PAGE    6

     263            ;--------------------------------------------------------------------------
     264 0032 738b                  LT      *,AR3   ; c4_gain in Q13 
     265                                            ; ARP = AR3. AR3 -> c4_out.
     266                                            ; AR2 -> FR1 (i.e. MASK)
     267            ;--------------------------------------------------------------------------
     268 0033 5480                  MPY     *       ; PREG = c4_gain *c4_out (Q13 x Q15 = Q28)
     269                                            ; ARP = AR3. AR3 -> c4_out.
     270                                            ; AR2 -> FR1 (i.e. MASK)
     271            ;--------------------------------------------------------------------------
     272 0034 be03                  PAC             ; Accumulator = c4_gain *c4_out
     273                                            ; ARP = AR3. AR3 -> c4_out.
     274                                            ; AR2 -> FR1 (i.e. MASK)
     275            ;--------------------------------------------------------------------------
     276 0035 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     277                                            ; ARP = AR3. AR3 -> a4_ch_sel.
     278                                            ;  AR2 -> FR1 (i.e. MASK)
     279            ;--------------------------------------------------------------------------            
     280             
     281 0036 be46                  CLRC    SXM     ; sign extension mode off
     282             
     283                ;Start another conversion
     284            
     285 0037       F243_ADC_Start_Next:
     286            
     287 0037 118a                  LACC    *,1,AR2 ; Accumulator = a4_ch_sel
     288                                            ; ARP = AR2.   AR2 -> FR1 (i.e. MASK) 
     289                                            ; AR3 -> a4_ch_sel. 
     290            ;--------------------------------------------------------------------------                                
     291 0038 bfb0                  AND     #000Eh  ; Accumulator= Accumulator & 000Eh
         0039 000e  
     292                                            ; ARP = AR2.   AR2 -> FR1 (i.e. MASK)
     293                                            ; AR3 -> a4_ch_sel. 
     294            ;--------------------------------------------------------------------------            
     295 003a 908b                  SACL    *,AR3   ; MASK = (a4_ch_sel*2) & (0x000E) 
     296                                            ; ARP = AR3. .  AR2 -> FR1 (i.e. MASK)
     297                                            ; AR3 -> a4_ch_sel. 
     298            ;--------------------------------------------------------------------------            
     299 003b 108a                  LACC    *,AR2   ; Accumulator = a4_ch_sel
     300                                            ; ARP = AR2. AR3 -> a4_ch_sel . 
     301                                            ; AR2 -> FR1 (i.e. MASK)
     302            ;--------------------------------------------------------------------------            
     303 003c bfb0                  AND     #0070h  ; Accumulator = a4_ch_sel & 0x0070
         003d 0070  
     304                                            ; ARP = AR2. AR3 -> a4_ch_sel .  
     305                                            ; AR2 -> FR1 (i.e. MASK)
     306            ;--------------------------------------------------------------------------            
     307 003e 6d8b                  OR      *,AR3   ; Accumulator = (a4_ch_sel & 0x0070) | MASK
     308                                            ; ARP = AR3. AR3 -> a4_ch_sel .  
     309                                            ; AR2 -> FR1 (i.e. MASK)
     310            ;--------------------------------------------------------------------------            
     311 003f bfc0                  OR      #1101100100000001b
         0040 d901  
     312                                    ;5432109876543210 
     313                                            ; Accumulator = 
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:44 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f243adc2.asm                                                         PAGE    7

     314                                            ;  ((a4_ch_sel & 0x0070) | MASK) | 0XD901)
     315                                            ; ARP = AR3. AR3 -> a4_ch_sel .  
     316                                            ; AR2 -> FR1 (i.e. MASK)
     317            ;--------------------------------------------------------------------------                        
     318 0041                       POINT_PF1
1        0041 bce0      LDP #0E0h
     319 0042 9032                  SACL    ADC_CNTL1
     320                                            ; Start 1st Dual conversion
     321                                            ; *ADC_CNTL1 = Accumulator
     322                                            ; ARP = AR3. AR3 -> a4_ch_sel .  
     323                                            ; AR2 -> FR1 (i.e. MASK)
     324            ;--------------------------------------------------------------------------            
     325 0043 198a                  LACC    *,9,AR2 ; Accumulator = a4_ch_sel<<9
     326                                            ; ARP = AR2. AR3 ->a4_ch_sel .  
     327                                            ; AR2 -> FR1 (i.e. MASK)
     328            ;--------------------------------------------------------------------------            
     329 0044 be81                  AND     #000Eh,16
         0045 000e  
     330                                            ; Accumulator = (a4_ch_sel<<9) & (0x000E<<16) 
     331                                            ; ARP = AR2. AR3 -> a4_ch_sel .  
     332                                            ; AR2 -> FR1 (i.e. MASK)
     333            ;--------------------------------------------------------------------------            
     334 0046 98ab                  SACH    *+,AR3  ; MASK = Most Significant Word 
     335                                            ; of Accumulator 
     336                                            ; ARP = AR3. AR3 -> a4_ch_sel. 
     337                                            ; AR2 -> FR2(i.e. GPR1ADC)
     338            ;--------------------------------------------------------------------------            
     339 0047 188a                  LACC    *,8,AR2 ; Accumulator = a4_ch_sel
     340                                            ; ARP = AR2. 
     341                                            ; AR2 -> FR2(i.e. GPR1ADC)
     342                                            
     343            ;---------------------------------------------------------------------------            
     344 0048 be81                  AND     #0070h,16
         0049 0070  
     345                                            ; Accumulator = (a4_ch_sel) & (0x0070 << 16)
     346                                            ; ARP = AR2. AR3 -> a4_ch_sel. 
     347                                            ; AR2 -> FR2(i.e. GPR1ADC)
     348                                           
     349            ;--------------------------------------------------------------------------            
     350 004a 9880                  SACH    *       ; GPR1ADC = Most Significant 
     351                                            ; Word Of Accumulator
     352                                            ; ARP = AR2. 
     353                                            ; AR2 -> FR2(i.e. GPR1ADC)
     354                                            
     355            ;--------------------------------------------------------------------------            
     356 004b 1090                  LACC    *-      ; Accumulator = GPR1ADC
     357                                            ; ARP = AR2. AR3 ->a4_ch_sel .  
     358                                            ; AR2 -> FR1 (i.e. MASK)
     359                                           
     360            ;--------------------------------------------------------------------------            
     361 004c 6d89                  OR      *,AR1   ; Accumulator = GPR1ADC | MASK
     362                                            ; Set ARP = AR1. in preparation for exit.
     363            ;-------------------------------------------------------------------------            
     364 004d bfc0                  OR  #1101100100000001b
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:44 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f243adc2.asm                                                         PAGE    8

         004e d901  
     365                                            ; Accumulator = GPR1ADC | MASK | 0xD901
     366                                            ; ARP = AR1.
     367            ;--------------------------------------------------------------------------                                    
     368 004f                       POINT_PF1  
1        004f bce0      LDP #0E0h
     369 0050 9032                  SACL    ADC_CNTL1
     370                                            ; ADC_CNTL2 = GPR1ADC | MASK | 0xD901
     371                                            ; Start 2nd Dual conversion
     372                           
     373              
     374 0051       __f243_adc_update_exit:
     375                            
     376                
     377 0051 7c04      SBRK    #(__F243_ADC_Update_framesize+1)
     378                                            ; deallocate frame, point to saved FP
     379 0052 0090      LAR     AR0, *-             ; restore frame pointer
     380 0053 7680      PSHD    *                   ; push return address on hardware stack
     381                               
     382 0054 ef00      RET
     383                               
     384                .end

 No Errors,  No Warnings