f243adc2.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     132                                            ; AR4 -> c1_gain.  
     133                                            ; AR2 -> FR1  (i.e. MASK)
     134            ;--------------------------------------------------------------------------                                
     135 000f be0a                  SFR             ; Right shift Accumulator 
     136                                            ; contents by one bit
     137                                            ; ARP = AR3. AR3 -> c1_gain.
     138                                            ; AR4 -> c1_gain
     139                                            ; AR2 -> FR1 (i.e. MASK)
     140            ;--------------------------------------------------------------------------                                
     141 0010 bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         0011 7fff  
     142                                            ; ARP = AR3. AR3 -> c1_gain. 
     143                                            ; AR4 -> c1_gain
     144                                            ; AR2 -> FR1 (i.e. MASK)
     145            ;--------------------------------------------------------------------------                                    
     146 0012 7804                  ADRK    #4      ; ARP = AR3. AR3 -> c1_out. 
     147                                            ; AR4 -> c1_gain. AR2 -> FR1 (i.e. MASK)
     148            ;--------------------------------------------------------------------------               
     149 0013 908c                  SACL    *,AR4   ; Accumulator = c1_out
     150                                            ; ARP = AR4. AR3 -> c1_out. 
     151                                            ; AR4 -> c1_gain. AR2 -> FR1 (i.e. MASK)
     152            ;--------------------------------------------------------------------------
     153 0014 73ab                  LT      *+,AR3  ; c1_gain in Q13 
     154                                            ; ARP = AR3. AR3 -> c1_out. 
     155                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     156            ;--------------------------------------------------------------------------
     157 0015 5480                  MPY     *       ; PREG = c1_gain * c1_out (Q13 x Q15 = Q28)
     158                                            ; ARP = AR3. AR3 -> c1_out. 
     159                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     160            ;--------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:44 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f243adc2.asm                                                         PAGE    4

     161 0016 be03                  PAC             ; Accumulator = c1_gain * c1_out
     162                                            ; ARP = AR3. AR3 -> c1_out. 
     163                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     164            ;--------------------------------------------------------------------------
     165 0017 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     166                                            ; ARP = AR3. AR3 -> c2_out. 
     167                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     168            ;--------------------------------------------------------------------------            
     169                          ;Read 2nd converted valu
     170            ;--------------------------------------------------------------------------
     171 0018                       POINT_PF1    
1        0018 bce0      LDP #0E0h
     172 0019 1038                  LACC    ADC_FIFO2
     173                                            ; Load Accumulator with ADC_FIFO2 status  
     174                                            ; ARP = AR3. AR3 -> c2_out. 
     175                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     176            ;--------------------------------------------------------------------------                                
     177 001a be0a                  SFR             ; Right shift Accumulator 
     178                                            ; contents by one bit
     179                                            ; ARP = AR3. AR3 -> c2_out. 
     180                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     181            ;--------------------------------------------------------------------------                                
     182 001b bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         001c 7fff  
     183                                            ; ARP = AR3. AR3 -> c2_out.
     184                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     185            ;--------------------------------------------------------------------------               
     186 001d 908c                  SACL    *,AR4   ; Accumulator = c2_out
     187                                            ; ARP = AR4. AR3 -> c2_out.
     188                                            ; AR4 -> c2_gain. AR2 -> FR1 (i.e. MASK)
     189            ;--------------------------------------------------------------------------
     190 001e 73ab                  LT      *+,AR3  ; c2_gain in Q13 T-> c2_gain
     191                                            ; ARP = AR3. AR3 -> c2_out.
     192                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     193            ;--------------------------------------------------------------------------
     194 001f 5480                  MPY     *       ; PREG = c2_gain *c2_out (Q13 x Q15 = Q28)
     195                                            ; ARP = AR3. AR3 -> c2_out.
     196                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     197            ;--------------------------------------------------------------------------
     198 0020 be03                  PAC             ; Accumulator = c2_gain *c2_out
     199                                            ; ARP = AR3. AR3 -> c2_out.
     200                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     201            ;--------------------------------------------------------------------------
     202 0021 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     203                                            ; ARP = AR3. AR3 -> c3_out.  
     204                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e MASK)
     205            ;--------------------------------------------------------------------------            
     206                   ;Read 3rd converted value
     207            ;--------------------------------------------------------------------------
     208 0022                       POINT_PF1    
1        0022 bce0      LDP #0E0h
     209 0023 1036                  LACC    ADC_FIFO1
     210                                            ; Load Accumulator with ADC_FIFO1 status 
     211                                            ; ARP = AR3. AR3 -> c3_out.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:44 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f243adc2.asm                                                         PAGE    5

     212                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     213            ;--------------------------------------------------------------------------                                
     214 0024 be0a                  SFR             ; Right shift Accumulator 
     215                                            ; contents by one bit
     216                                            ; ARP = AR3. AR3 -> c3_out.
     217                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     218            ;--------------------------------------------------------------------------                                
     219 0025 bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         0026 7fff  
     220                                            ; ARP = AR3. AR3 -> c3_out.
     221                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     222            ;--------------------------------------------------------------------------               
     223 0027 908c                  SACL    *,AR4   ; Accumulator = c3_out
     224                                            ; ARP = AR4. AR3 -> c3_out.
     225                                            ; AR4 -> c3_gain. AR2 -> FR1 (i.e. MASK)
     226            ;--------------------------------------------------------------------------
     227 0028 73ab                  LT      *+,AR3  ; c3_gain in Q13 T->c3_gain
     228                                            ; ARP = AR3. AR3 -> c3_out.
     229                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     230            ;--------------------------------------------------------------------------
     231 0029 5480                  MPY     *       ; PREG = c3_gain *c3_out (Q13 x Q15 = Q28)
     232                                            ; ARP = AR3. AR3 -> c3_out.
     233                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     234            ;--------------------------------------------------------------------------
     235 002a be03                  PAC             ; Accumulator = c1_gain *c1_out
     236                                            ; ARP = AR3. AR3 -> c3_out.
     237                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     238            ;--------------------------------------------------------------------------
     239 002b 9ba0                  SACH    *+,3    ; Convert final result to Q15 
     240                                            ; ARP = AR3. AR3 -> c4_out.
     241                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     242            ;--------------------------------------------------------------------------            
     243                   ;Read 4th converted value
     244            ;--------------------------------------------------------------------------
     245 002c                       POINT_PF1    
1        002c bce0      LDP #0E0h
     246 002d 1038                  LACC    ADC_FIFO2
     247                                            ; Load Accumulator with ADC_FIFO2 status  
     248                                            ; ARP = AR3. AR3 -> c4_out.
     249                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     250            ;--------------------------------------------------------------------------                                
     251 002e be0a                  SFR             ; Right shift Accumulator 
     252                                            ; contents by one bit
     253                                            ; ARP = AR3. AR3 -> c4_out.
     254                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     255            ;--------------------------------------------------------------------------                                
     256 002f bfb0                  AND     #7FFFh  ; Accumulator = Accumulator & 7FFFh
         0030 7fff  
     257                                            ; ARP = AR3. AR3 -> c4_out.
     258                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)
     259            ;--------------------------------------------------------------------------               
     260 0031 908c                  SACL    *,AR4   ; Accumulator = c4_out
     261                                            ; ARP = AR4. AR3 -> c4_out.
     262                                            ; AR4 -> c4_gain. AR2 -> FR1 (i.e. MASK)