f2407ilg1.asm

TI的digital motor control lib的源代码。了解TI的编程规范

*******************************************************
* TMS320C2x/C2xx/C5x ANSI C Codegen Version 7.00       
*******************************************************
;	C:\TIC2XX\C2000\CGTOOLS\BIN\DSPAC.EXE -v2xx -q f2407ilg1.c C:\WINDOWS\TEMP\f2407ilg1.if 
;	dspopt NOT RUN
;	C:\TIC2XX\C2000\CGTOOLS\BIN\DSPCG.EXE -v2xx -o -q -o C:\WINDOWS\TEMP\f2407ilg1.if C:\WINDOWS\TEMP\f2407ilg1.asm C:\WINDOWS\TEMP\f2407ilg1.tmp 
	.port
	.file	"f2407ilg1.c"
	.file	"..\include\regs240x.h"
	.globl	_portffff
	.globl	_portff0f
	.globl	_port0
	.globl	_port1
	.globl	_port2
	.globl	_port3
	.globl	_port4
	.file	"..\include\F2407ILG.h"

	.stag	.fake0,160
	.member	_gain_a,0,4,8,16
	.member	_offset_a,16,4,8,16
	.member	_out_a,32,4,8,16
	.member	_gain_b,48,4,8,16
	.member	_offset_b,64,4,8,16
	.member	_out_b,80,4,8,16
	.member	_ch_a,96,4,8,16
	.member	_ch_b,112,4,8,16
	.member	_init,128,148,8,16
	.member	_read,144,148,8,16
	.eos
	.sym	_ILEG2MEAS,0,8,13,160,.fake0
	.globl	_F2407_leg2_drv_init
	.globl	_F2407_leg2_drv_read
	.file	"f2407ilg1.c"
	.text

	.sym	_F2407_leg2_drv_init,_F2407_leg2_drv_init,32,2,0
	.globl	_F2407_leg2_drv_init

	.func	42
;>>>> 	void inline F2407_leg2_drv_init(ILEG2MEAS *p)
******************************************************
* FUNCTION DEF : _F2407_leg2_drv_init
******************************************************
_F2407_leg2_drv_init:

LF1	.set	0

	POPD	*+
	SAR	AR0,*+
	SAR	AR1,*
	LARK	AR0,1
	LAR	AR0,*0+,AR3

	.sym	_p,-3+LF1,24,9,16,.fake0
	.line	2
	.line	4
;>>>> 	        SCSR1=SCSR1|0x0080;                 /* Turn on the clocks to the ADC module*/
	LARK	AR3,28696
	LACK	128
	OR	* 
	SACL	* 
	.line	5
;>>>> 	        CALIBRATION=CALIBRATION_CONSTANT;
	LACK	0
	ADRK	160
	SACL	* ,AR4
	.line	7
;>>>> 	        GPTCONA=((GPTCONA&0xfe7f)|0x0080);   /* Set up EV Trigger              */
	LARK	AR4,29696
	LACK	65151
	AND	* 
	ORK	128
	SACL	* ,AR3
	.line	8
;>>>> 	        ADCTRL1=ADC_RESET_FLAG;             /* Reset the ADC Module           */
	SBRK	24
	SPLK	#16384,* 
	.line	9
;>>>> 	        ADCTRL1=ADCTRL1_INIT_STATE;         /* Set up ADCTRL1 and 2 registers */
	SPLK	#12288,*+
	.line	10
;>>>> 	        ADCTRL2=ADCTRL2_INIT_STATE;
	SPLK	#770,*+
	.line	11
;>>>> 	        MAXCONV=1;                          /* Specify two conversions        */
	LACK	1
	SACL	* ,AR2
	.line	14
;>>>> 	        CHSELSEQ1=((p->ch_b)<<4)+(  p->ch_a ) ;
	LARK	AR2,-3+LF1
	MAR	*0+
	LAR	AR5,* 
	LAR	AR4,* ,AR5
	ADRK	6
	LAC	* ,AR4
	ADRK	7
	ADD	* ,4,AR3
	MAR	*+
	SACL	* ,AR1
EPI0_1:
	.line	20
	SBRK	2
	LAR	AR0,*-
	PSHD	*
	RET

	.endfunc	61,000000000H,1
	.end