f07ilvd2.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     103            ;--------------------------------------------------------------------------------
     104 0017 54a0          MPY     *+      ; PREG = Imeas_a_gain*Imeas_a (Q28)
     105                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_a_offset, AR3->RESULT0
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f07ilvd2.asm                                                         PAGE    3

     106            ;--------------------------------------------------------------------------------
     107 0018 be03          PAC             ; ACC = Imeas_a_gain*Imeas_a (Q28) 
     108                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_a_offset, AR3->RESULT0
     109            ;--------------------------------------------------------------------------------
     110 0019 2da0          ADD     *+,13   ; ACC = Imeas_a_gain*Imeas_a + Imeas_a_offset  (Q28)
     111                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT0
     112            ;--------------------------------------------------------------------------------
     113 001a be02                  NEG                             ; Positive direction, current flows to motor
     114                                                            ; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT0 
     115            ;--------------------------------------------------------------------------------
     116 001b 9bab          SACH    *+,3,AR3 ; Imeas_a = Imeas_a_gain*Imeas_a + Imeas_a_offset (Q15) 
     117                                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT0, ARP=AR3   
     118            ;--------------------------------------------------------------------------------
     119 001c 7801          ADRK    #1      ; ARP=AR3, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
     120            ;--------------------------------------------------------------------------------
     121 001d 1088          LACC    *,AR0   ; ACC = ADC_RESULT1 (raw data)
     122                                    ; ARP=AR3, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1, ARP=AR0
     123            ;--------------------------------------------------------------------------------
     124 001e bfd0          XOR     #8000h  ; Convert result to Q15 (bipolar signal)
         001f 8000  
     125                                    ; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
     126            ;--------------------------------------------------------------------------------
     127 0020 9080          SACL    *       ; FR0 = Imeas_b  (Q15)
     128                                    ; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
     129            ;--------------------------------------------------------------------------------
     130 0021 738a          LT      *,AR2   ; TREG = Imeas_b (Q15)
     131                                    ; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1, ARP=AR2
     132            ;--------------------------------------------------------------------------------
     133 0022 54a0          MPY     *+      ; PREG = Imeas_b_gain*Imeas_b (Q28)
     134                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_b_offset, AR3->RESULT1
     135            ;--------------------------------------------------------------------------------
     136 0023 be03          PAC             ; ACC = Imeas_b_gain*Imeas_b (Q28) 
     137                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_b_offset, AR3->RESULT1
     138            ;--------------------------------------------------------------------------------
     139 0024 2da0          ADD     *+,13   ; ACC = Imeas_b_gain*Imeas_b + Imeas_b_offset  (Q28)
     140                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT1
     141            ;--------------------------------------------------------------------------------
     142 0025 be02                  NEG                             ; Positive direction, current flows to motor
     143                                                            ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT1 
     144            ;--------------------------------------------------------------------------------
     145 0026 9bab          SACH    *+,3,AR3 ; Imeas_b = Imeas_b_gain*Imeas_b + Imeas_b_offset (Q15)
     146                                                    ; ARP=AR2, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT1, ARP=AR3
     147            ;--------------------------------------------------------------------------------
     148 0027 7801          ADRK    #1      ; ARP=AR3, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
     149            ;--------------------------------------------------------------------------------
     150 0028 1088          LACC    *,AR0   ; ACC = ADC_RESULT2 (raw data)
     151                                    ; ARP=AR3, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2, ARP=AR0
     152            ;--------------------------------------------------------------------------------
     153 0029 be0a          SFR                     ; Convert result to Q15 (unipolar signal)
     154                                    ; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
     155            ;-------------------------------------------------------------------------------
     156 002a bfb0                  AND             #7FFFh  ; Convert result to Q15 (unipolar signal)
         002b 7fff  
     157                                    ; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2 
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:42:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
f07ilvd2.asm                                                         PAGE    4

     158            ;-------------------------------------------------------------------------------
     159 002c 9080          SACL    *               ; FR0 = Vdc_meas (Q15)
     160                                                    ; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2   
     161            ;--------------------------------------------------------------------------------
     162 002d 738a          LT      *,AR2   ; TREG = Vdc_meas (Q15)
     163                                    ; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2, ARP=AR2
     164            ;--------------------------------------------------------------------------------
     165 002e 54a0          MPY     *+      ; PREG = Vdc_meas_gain*Vdc_meas (Q28)
     166                                    ; ARP=AR2, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
     167            ;--------------------------------------------------------------------------------
     168 002f be03          PAC             ; ACC = Vdc_meas_gain*Vdc_meas (Q28) 
     169                                    ; ARP=AR2, AR0->FR0, AR2->Vdc_meas_offset, AR3->RESULT2
     170            ;--------------------------------------------------------------------------------
     171 0030 2da0          ADD     *+,13   ; ACC = Vdc_meas_gain*Vdc_meas + Vdc_meas_offset  (Q28)
     172                                    ; ARP=AR2, AR0->FR0, AR2->Vdc_meas, AR3->RESULT2
     173            ;-------------------------------------------------------------------------------
     174 0031 9b80          SACH    *,3     ; Vdc_meas = Vdc_meas_gain*Vdc_meas + Vdc_meas_offset (Q15)
     175                                                    ; ARP=AR2, AR0->FR0, AR2->Vdc_meas, AR3->RESULT2
     176            ;-------------------------------------------------------------------------------
     177 0032 7c06          SBRK    #6              ; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT2
     178            ;--------------------------------------------------------------------------------
     179 0033 1080                  LACC    *               ; ACC = Imeas_a  (Q15)
     180                                                            ; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT2
     181            ;-------------------------------------------------------------------------------
     182 0034 7803                  ADRK    #3              ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2
     183            ;-------------------------------------------------------------------------------
     184 0035 2080                  ADD             *               ; ACC = Imeas_a + Imeas_b (Q15)
     185                                                            ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2 
     186            ;-------------------------------------------------------------------------------
     187 0036 be02          NEG                             ; ACC = -(Imeas_a + Imeas_b)  (Q15)
     188                                                    ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2  
     189            ;-------------------------------------------------------------------------------
     190 0037 7804                  ADRK    #4              ; ARP=AR2, AR0->FR0, AR2->Imeas_c, AR3->RESULT2 
     191            ;-------------------------------------------------------------------------------
     192 0038 9089                  SACL    *,AR1   ; Imeas_c = -(Imeas_a + Imeas_b)  (Q15)
     193                                                            ; ARP=AR2, AR0->FR0, AR2->Imeas_c, AR3->RESULT2, ARP=AR1 
     194            ;-------------------------------------------------------------------------------
     195 0039       _F2407_ileg2_dcbus_drv_read_exit:
     196                    ;MAR    *,AR1   ; can be removed if this condition is met on
     197                    ;                ; every path to this code. (i.e., ARP=AR1 here)
     198                    
     199 0039 7c02          SBRK    #(__F2407_ileg2_dcbus_drv_read_framesize+1)
     200 003a 0090          LAR     AR0,*-
     201 003b 7680          PSHD    *
     202 003c ef00          RET
     203            
     204            

 No Errors,  No Warnings