svgen_dq.asm

TI的digital motor control lib的源代码。了解TI的编程规范

;=====================================================================================
; File name:        SVGEN_DQ.ASM                      
;                    
; Originator:	Digital Control Systems Group
;			Texas Instruments
;
; Description:                                 
; This file contains source for Space vector modulation dq -> SV(a,b,c).
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000	Release	Rev 1.0
;================================================================================
; Applicability: F240,F241,C242,F243,F24xx.  (Peripheral Independant).
;================================================================================
; Routine Name: svgendq                                Routine Type: C Callable
;
; Description:
;  
;  C prototype : int svgendq(struct SVGENDQ *p);
;
;        The struct is defined as follows:
;
;        typedef struct SVGENDQ { int d,q,ta,tb,tc ; };
;
;        Frame Usage Details:
;            |      a      |      b        |   c        |     d     
;____________|_____________|_______________|____________|_____________
;       FR0  |    va       |      X        |    X       |     X
;       FR1  |    vb       |      Y        |    Y       |     Y
;       FR2  |    vc       |      Z        |    Z       |     Z
;       FR3  |  sector     |   sector      | sr_address |     t1
;       FR4  |             |               |            |     t2

                                

;================================================================================
                .def        _svgendq_calc
;================================================================================
__svgendq_framesize .set 0005h
;================================================================================
_svgendq_calc:
                     POPD        *+
                SAR        AR0,*+
                SAR        AR1,*
                LARK        AR0,__svgendq_framesize
                LAR        AR0,*0+,AR0

;================================================================================
                SBRK        #3        ; Point AR0 to the first argument.
;--------------------------------------------------------------------------------
                LAR        AR2,*
                                ; get the argument in AR2.
                                ; ARP=AR0. AR0->([FR0-3]=Argument 1) and AR2->d
                ADRK    #3      ; ARP=AR0. AR0->FR0 and AR2->d

                MAR     *,AR2   ; ARP=AR2. AR0->FR0 and AR2->d
;--------------------------------------------------------------------------------
                SPM     1       ; Set product shift mode to one.
                                ; ARP=AR2. AR0->FR0 and AR2->d
;--------------------------------------------------------------------------------
                SETC    SXM     ; Turn sign extension mode on.
                                ; ARP=AR2. AR0->FR0 and AR2->d

;--------------------------------------------------------------------------------
                ADRK    #1      ; ARP=AR2. AR0->FR0 and AR2->q
;--------------------------------------------------------------------------------
                LACC    *-,AR0  ; Load q.
                                ; ARP=AR0. AR0->FR0 and AR2->d
;--------------------------------------------------------------------------------
                SACL    *+      ; Store va=q
                                ; ARP=AR0. AR0->FR1 and AR2->d
;--------------------------------------------------------------------------------
                SPLK    #28377,*
                                ; FR1 = 0.5*qrt3.
                                ; ARP=AR0. AR0->FR1 and AR2->d
;--------------------------------------------------------------------------------
                LT      *,AR2   ; TREG = 0.5*qrt3.
                                ; ARP=AR2. AR0->FR1 and AR2->d
;--------------------------------------------------------------------------------
                MPY     *+      ; PREG = d * 0.5sqrt(3).
                                ; ARP=AR2. AR0->FR1 and AR2->q
;--------------------------------------------------------------------------------
                ZAC             ; ACCH:ACCL=0.
                                ; ARP=AR2. AR0->FR1 and AR2->q
;--------------------------------------------------------------------------------
                SUB     *,15,AR0 ;ACC = -q/2
                                ; ARP=AR0. AR0->FR1 and AR2->q
;--------------------------------------------------------------------------------
                APAC            ; ACC = -q/2 +  d * 0.5sqrt(3)
                                ; ARP=AR0. AR0->FR1 and AR2->q
;--------------------------------------------------------------------------------
                SACH    *+      ; Store vb.
                                ; ARP=AR0. AR0->FR2 and AR2->q
;--------------------------------------------------------------------------------
                SPAC            ; ACC = -q/2 
                                ; ARP=AR0. AR0->FR2 and AR2->q
;--------------------------------------------------------------------------------
                SPAC            ; ACC = -q/2 - (d * 0.5sqrt(3))
                                ; ARP=AR0. AR0->FR2 and AR2->q
;--------------------------------------------------------------------------------
                SACH    *+      ; Store vc.
                                ; ARP=AR0. AR0->FR3 and AR2->q
;--------------------------------------------------------------------------------
                SAR     AR0,*   ; FR3 = AR0 = &FR3.
                                ; ARP=AR0. AR0->FR3 and AR2->q
;--------------------------------------------------------------------------------
                LAR     AR3,*-,AR3
                                ; AR3 = FR3 = &FR3.                
                                ; i.e. now AR3 points to FR3.
                                ; ARP=AR3. AR0->FR2 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                SPLK    #0,*,AR0
                                ; Store sector = FR3 = 0
                                ; ARP=AR0. AR0->FR2 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *-      ; Load vc.
                                ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                BCND    vref3_neg,LEQ
                                ; If vc<0 then do not set bit 2 of sector.
                                ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                MAR     *,AR3   ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *       ; Get sector code.
                                ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                OR      #4      ; Set bit 2.
                                ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                SACL    *,AR0   ; Store sector code
                                ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
vref3_neg:      LACC    *-      ; Load vb
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                BCND    vref2_neg,LEQ
                                ; If vb<0 then do not set bit 1 of sector.
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                MAR     *,AR3   ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *       ; Get sector code.
                                ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                OR      #2      ; Set bit 1.
                                ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                SACL    *,AR0   ; Store sector code
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3

vref2_neg:      LACC    *       ; Load va
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                BCND    vref1_neg,LEQ
                                ; If vb<0 then do not set bit 1 of sector.
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                MAR     *,AR3   ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *       ; Get sector code.
                                ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                OR      #1      ; Set bit 0.
                                ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                SACL    *,AR0   ; Store sector code
                                ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
vref1_neg:                      

;--------------------------------------------------------------------------------
                MAR     *,AR2   ; ARP=AR2. AR0->FR0 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *-,AR0  ; ACC = q.
                                ; ARP=AR0. AR0->FR0 AR2->d AR3->FR3
;--------------------------------------------------------------------------------
                SACL    *+      ; Store FR0=X=q.
                                ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
;--------------------------------------------------------------------------------
                SPLK    #28377,* ;FR1 = sqrt(3) / 2.
                                ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
;--------------------------------------------------------------------------------
                LT      *,AR2   ; TREG = sqrt(3) / 2.
                                ; ARP=AR2. AR0->FR1 AR2->d AR3->FR3
;--------------------------------------------------------------------------------
                MPY     *+      ; PREG = d * sqrt(3) / 2.
                                ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                PAC             ; ACC = d * sqrt(3) / 2.
                                ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                ADD     *,15,AR0 ; ACCH= q/2 + d * sqrt(3) / 2.
                                ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                SACH    *+,AR2  ; Store FR1 = Y = q/2 + d * sqrt(3) / 2.
                                ; ARP=AR2. AR0->FR2 AR2->q AR3->FR3
;--------------------------------------------------------------------------------
                LACC    *+,15,AR0 ; ACCH = q/2.
                                ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
;--------------------------------------------------------------------------------
                SPAC            ; ACCH = q/2 - d * sqrt(3) / 2.