speed_fr.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     100            ;----------------------------------------------------------------------------------
     101 0018 7980          B               SKIP_DIFF_FR  ; ARP=AR2, AR0->FR0, AR2->theta_elec
         0019 002d' 
     102            ;----------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:26 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
speed_fr.asm                                                         PAGE    3

     103 001a       MORE_MIN_FR                             ; ARP=AR2, AR0->FR0, AR2->theta_elec
     104            ;----------------------------------------------------------------------------------
     105 001a 73a0          LT              *+              ; TREG = theta_elec  (Q15)
     106                                                    ; ARP=AR2, AR0->FR0, AR2->K1_fr 
     107            ;----------------------------------------------------------------------------------
     108 001b 54a0                  MPY             *+              ; PREG = K1_fr*theta_elec  (Q21)
     109                                                    ; ARP=AR2, AR0->FR0, AR2->theta_old
     110            ;----------------------------------------------------------------------------------
     111 001c be03                  PAC                             ; ACC = K1_fr*theta_elec  (Q21)
     112                                                    ; ARP=AR2, AR0->FR0, AR2->theta_old
     113            ;----------------------------------------------------------------------------------
     114 001d 7390          LT              *-              ; TREG = theta_old  (Q15)
     115                                                    ; ARP=AR2, AR0->FR0, AR2->K1_fr
     116            ;----------------------------------------------------------------------------------
     117 001e 5488          MPY             *,AR0   ; PREG = K1_fr*theta_old  (Q21)
     118                                                    ; ARP=AR2, AR0->FR0, AR2->K1_fr, ARP=AR0
     119            ;----------------------------------------------------------------------------------
     120 001f be05          SPAC                    ; ACC = K1_fr*theta_elec-K1_fr*theta_old  (Q21)
     121                                                    ; ARP=AR0, AR0->FR0, AR2->K1_fr
     122            ;----------------------------------------------------------------------------------
     123 0020 be09                  SFL                             ; ACC = K1_fr*theta_elec-K1_fr*theta_old  (Q22)
     124                                                    ; ARP=AR0, AR0->FR0, AR2->K1_fr
     125            ;----------------------------------------------------------------------------------
     126 0021 be09                  SFL                             ; ACC = K1_fr*theta_elec-K1_fr*theta_old  (Q23)
     127                                                    ; ARP=AR0, AR0->FR0, AR2->K1_fr
     128            ;----------------------------------------------------------------------------------
     129 0022 be09                  SFL                             ; ACC = K1_fr*theta_elec-K1_fr*theta_old  (Q24)
     130                                                    ; ARP=AR0, AR0->FR0, AR2->K1_fr
     131            ;----------------------------------------------------------------------------------
     132 0023 9f8a          SACH    *,7,AR2 ; FR0 = tmp1 = K1_fr*theta_elec-K1_fr*theta_old  (Q15)
     133                                                    ; ARP=AR0, AR0->FR0, AR2->K1_fr, ARP=AR2
     134            ;----------------------------------------------------------------------------------
     135 0024 7802          ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->K2_fr                 
     136            ;----------------------------------------------------------------------------------
     137 0025 73a0                  LT              *+              ; TREG = K2_fr  (Q15)
     138                                                            ; ARP=AR2, AR0->FR0, AR2->speed_frq 
     139            ;----------------------------------------------------------------------------------
     140 0026 54a0                  MPY             *+              ; PREG = K2_fr*speed_frq  (Q30)
     141                                                            ; ARP=AR2, AR0->FR0, AR2->K3_fr
     142            ;----------------------------------------------------------------------------------
     143 0027 be03          PAC                             ; ACC = K2_fr*speed_frq  (Q30)
     144                                                            ; ARP=AR2, AR0->FR0, AR2->K3_fr
     145            ;----------------------------------------------------------------------------------
     146 0028 7398                  LT              *-,AR0  ; TREG = K3_fr  (Q15)
     147                                                            ; ARP=AR2, AR0->FR0, AR2->speed_frq, ARP=AR0 
     148            ;----------------------------------------------------------------------------------
     149 0029 548a                  MPY             *,AR2   ; PREG = K2_fr*speed_frq  (Q30)
     150                                                            ; ARP=AR0, AR0->FR0, AR2->speed_frq, ARP=AR2            
     151            ;----------------------------------------------------------------------------------
     152 002a be04                  APAC                    ; ACC = K2_fr*speed_frq + K2_fr*speed_frq (Q30)
     153                                                            ; ARP=AR2, AR0->FR0, AR2->speed_frq
     154            
     155            ;----------------------------------------------------------------------------------
     156 002b 9980                  SACH    *,1             ; speed_frq = K2_fr*speed_frq + K2_fr*speed_frq (Q15)
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:26 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
speed_fr.asm                                                         PAGE    4

     157                                                            ; ARP=AR2, AR0->FR0, AR2->speed_frq
     158            ;----------------------------------------------------------------------------------
     159 002c 7c04          SBRK    #4              ; ARP=AR2, AR0->FR0, AR2->theta_elec
     160            ;----------------------------------------------------------------------------------
     161 002d       SKIP_DIFF_FR                    ; ARP=AR2, AR0->FR0, AR2->theta_elec
     162            ;----------------------------------------------------------------------------------
     163 002d 1080          LACC    *               ; ACC = theta_r_se  (Q15)
     164                                                    ; ARP=AR2, AR0->FR0, AR2->theta_elec
     165            ;----------------------------------------------------------------------------------
     166 002e 7802          ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->theta_old
     167            ;----------------------------------------------------------------------------------
     168 002f 9080          SACL    *               ; theta_old = theta_elec  (Q15)
     169                                                    ; ARP=AR2, AR0->FR0, AR2->theta_old
     170            ;----------------------------------------------------------------------------------
     171 0030 7802          ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->speed_frq
     172            ;----------------------------------------------------------------------------------
     173 0031 7380                  LT              *               ; TREG = speed_frq (Q15)
     174                                                            ; ARP=AR2, AR0->FR0, AR2->speed_frq
     175            ;----------------------------------------------------------------------------------
     176 0032 7802                  ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->rpm_max
     177            ;----------------------------------------------------------------------------------
     178 0033 54a0                  MPY             *+              ; PREG = speed_frq*rpm_max  (Q15)
     179                                                            ; ARP=AR2, AR0->FR0, AR2->speed_rpm
     180            ;----------------------------------------------------------------------------------
     181 0034 be03                  PAC                             ; ACC = speed_frq*rpm_max  (Q15)
     182                                                            ; ARP=AR2, AR0->FR0, AR2->speed_rpm
     183            ;----------------------------------------------------------------------------------
     184 0035 9989                  SACH    *,1,AR1 ; speed_rpm = speed_frq*rpm_max  (Q0)
     185                                                            ; ARP=AR2, AR0->FR0, AR2->speed_rpm, ARP=AR1
     186            ;----------------------------------------------------------------------------------
     187 0036       SPEED_FRQ_END
     188            ;----------------------------------------------------------------------------------
     189 0036       __speed_frq_exit:
     190                            ;;;MAR     *,AR1   ; can be removed if this condition is met on
     191                                   ; every path to this code. (i.e., ARP=AR1 here)
     192                    
     193 0036 be46          CLRC    SXM
     194 0037 be42          CLRC    OVM
     195 0038 bf00          SPM             0
     196                                   
     197 0039 7c02          SBRK    #(__speed_frq_framesize+1)
     198 003a 0090          LAR     AR0,*-
     199 003b 7680          PSHD    *
     200 003c ef00          RET
     201            

 No Errors,  No Warnings