📄 pid_reg1.lst
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158 ;----------------------------------------------------------------------------------
159 0029 1080 LACC * ; ACC = sign_reg1 (pid_e0_reg1)
160 ; ARP=AR0, AR0->FR0, AR2->Kp_reg1
161 ;----------------------------------------------------------------------------------
162 002a 7803 ADRK #3 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 4
163 ;----------------------------------------------------------------------------------
164 002b e304 BCND DONE_REG1,GT ; Check sign = positive ?
002c 0032'
165 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
166 ;----------------------------------------------------------------------------------
167 002d 6a90 LACC *-,16 ; ACC high = tmp2_high_reg1
168 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
169 ;----------------------------------------------------------------------------------
170 002e 6280 ADDS * ; ACC = tmp2_high_reg1 + tmp2_low_reg1
171 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
172 ;----------------------------------------------------------------------------------
173 002f be02 NEG ; Make the result negative
174 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
175 ;----------------------------------------------------------------------------------
176 0030 90a0 SACL *+ ; tmp2_low_reg1 = ACC high (Q31)
177 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
178 ;----------------------------------------------------------------------------------
179 0031 9880 SACH * ; tmp2_high_reg1 = ACC low (Q31)
180 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
181 ;----------------------------------------------------------------------------------
182 0032 DONE_REG1
183 ;----------------------------------------------------------------------------------
184 0032 8baa MAR *+,AR2 ; ARP=AR0, AR0->FR4, AR2->Kp_reg1, ARP=AR2
185 ;----------------------------------------------------------------------------------
186 0033 7803 ADRK #3 ; ARP=AR2, AR0->FR4, AR2->K2_reg1 (Kd_reg1)
187 ;----------------------------------------------------------------------------------
188 0034 7380 LT * ; TREG = K2_reg1 (Q15)
189 ; ARP=AR2, AR0->FR4, AR2->K2_reg1
190 ;----------------------------------------------------------------------------------
191 0035 7804 ADRK #4 ; ARP=AR2, AR0->FR4, AR2->pid_e2_reg1
192 ;----------------------------------------------------------------------------------
193 0036 5490 MPY *- ; PREG = K2_reg1*pid_e2_reg1 (Q30)
194 ; ARP=AR2, AR0->FR4, AR2->pid_e1_reg1
195 ;----------------------------------------------------------------------------------
196 0037 be03 PAC ; ACC = K2_reg1*pid_e2_reg1 (Q30)
197 ; ARP=AR2, AR0->FR4, AR2->pid_e1_reg1
198 ;----------------------------------------------------------------------------------
199 0038 7388 LT *,AR0 ; TREG = pid_e1_reg1 (Q15)
200 ; ARP=AR2, AR0->FR4, AR2->pid_e1_reg1, ARP=AR0
201 ;----------------------------------------------------------------------------------
202 0039 5490 MPY *- ; PREG = K1_reg1*pid_e1_reg1 (Q30)
203 ; ARP=AR0, AR0->FR3, AR2->pid_e1_reg1
204 ;----------------------------------------------------------------------------------
205 003a be05 SPAC ; ACC = -K1_reg1*pid_e1_reg1 + K2_reg1*pid_e2_reg1 (Q30)
206 ; ARP=AR0, AR0->FR3, AR2->pid_e1_reg1
207 ;----------------------------------------------------------------------------------
208 003b be09 SFL ; ACC = -K1_reg1*pid_e1_reg1 + K2_reg1*pid_e2_reg1 (Q31)
209 ; ARP=AR0, AR0->FR3, AR2->pid_e1_reg1
210 ;----------------------------------------------------------------------------------
211 003c 6190 ADDH *- ; ACC high = ACC high + tmp2_high_reg1 (Q31)
212 ; ARP=AR0, AR0->FR2, AR2->pid_e1_reg1
213 ;----------------------------------------------------------------------------------
214 003d 629a ADDS *-,AR2 ; ACC low = ACC low + tmp2_low_reg1 (Q31)
215 ; ARP=AR0, AR0->FR1, AR2->pid_e1_reg1, ARP=AR2
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 5
216 ;----------------------------------------------------------------------------------
217 003e 7802 ADRK #2 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
218 ;----------------------------------------------------------------------------------
219 003f 6180 ADD *,16 ; ACC = ACC + pid_out_reg1 (Q15)
220 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
221 ;----------------------------------------------------------------------------------
222 0040 9880 SACH * ; pid_out_reg1 = ACC + pid_out_reg1 (Q15)
223 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
224 ;----------------------------------------------------------------------------------
225 0041 1080 LACC * ; ACC = pid_out_reg1 (Q15)
226 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
227 ;----------------------------------------------------------------------------------
228 0042 7c04 SBRK #4 ; ARP=AR2, AR0->FR1, AR2->pid_out_max
229 ;----------------------------------------------------------------------------------
230 0043 3080 SUB * ; ACC = pid_out_reg1 - pid_out_max (Q15)
231 ; ARP=AR2, AR0->FR1, AR2->pid_out_max
232 ;----------------------------------------------------------------------------------
233 0044 e304 BCND SAT_MAX,GT ; Branch if saturated at max
0045 0054'
234 ; ARP=AR2, AR0->FR1, AR2->pid_out_max
235 ;----------------------------------------------------------------------------------
236 0046 7804 ADRK #4 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
237 ;----------------------------------------------------------------------------------
238 0047 1080 LACC * ; ACC = pid_out_reg1 (Q15)
239 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
240 ;----------------------------------------------------------------------------------
241 0048 7c03 SBRK #3 ; ARP=AR2, AR0->FR1, AR2->pid_out_min
242 ;----------------------------------------------------------------------------------
243 0049 3080 SUB * ; ACC = pid_out_reg1 - pid_out_min (Q15)
244 ; ARP=AR2, AR0->FR1, AR2->pid_out_min
245 ;----------------------------------------------------------------------------------
246 004a e344 BCND SAT_MIN,LT ; Branch if saturated at min
004b 004f'
247 ; ARP=AR2, AR0->FR1, AR2->pid_out_min
248 ;----------------------------------------------------------------------------------
249 004c 7803 ADRK #3 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
250 ;----------------------------------------------------------------------------------
251 004d 7980 B REG1_END ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
004e 0057'
252 ;----------------------------------------------------------------------------------
253 004f SAT_MIN
254 ;----------------------------------------------------------------------------------
255 004f 1080 LACC * ; ACC = pid_out_min (Q15)
256 ; ARP=AR2, AR0->FR1, AR2->pid_out_min
257 ;----------------------------------------------------------------------------------
258 0050 7803 ADRK #3 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
259 ;----------------------------------------------------------------------------------
260 0051 9080 SACL * ; pid_out_reg1 = pid_out_min (Q15)
261 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
262 ;----------------------------------------------------------------------------------
263 0052 7980 B REG1_END ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
0053 0057'
264 ;----------------------------------------------------------------------------------
265 0054 SAT_MAX
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 6
266 ;----------------------------------------------------------------------------------
267 0054 1080 LACC * ; ACC = pid_out_max (Q15)
268 ; ARP=AR2, AR0->FR1, AR2->pid_out_max
269 ;----------------------------------------------------------------------------------
270 0055 7804 ADRK #4 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
271 ;----------------------------------------------------------------------------------
272 0056 9080 SACL * ; pid_out_reg1 = pid_out_max (Q15)
273 ; ARP=AR2, AR0->FR1, AR2->pid_out_reg1
274 ;----------------------------------------------------------------------------------
275 0057 REG1_END
276 ;----------------------------------------------------------------------------------
277 0057 7c02 SBRK #2 ; ARP=AR2, AR0->FR1, AR2->pid_e1_reg1
278 ;----------------------------------------------------------------------------------
279 0058 10a0 LACC *+ ; ACC = pid_e1_reg1 (Q15)
280 ; ARP=AR2, AR0->FR1, AR2->pid_e2_reg1
281 ;----------------------------------------------------------------------------------
282 0059 9098 SACL *-,AR0 ; pid_e2_reg1 = pid_e1_reg1 (Q15)
283 ; ARP=AR2, AR0->FR1, AR2->pid_e1_reg1, ARP=AR0
284 ;----------------------------------------------------------------------------------
285 005a 7c01 SBRK #1 ; ARP=AR0, AR0->FR0, AR2->pid_e1_reg1
286 ;----------------------------------------------------------------------------------
287 005b 108a LACC *,AR2 ; ACC = FR0 = pid_e0_reg1 (sign_reg1) (Q15)
288 ; ARP=AR0, AR0->FR0, AR2->pid_e1_reg1, ARP=AR2
289 ;----------------------------------------------------------------------------------
290 005c 9089 SACL *,AR1 ; pid_e1_reg1 = pid_e0_reg1 (Q15)
291 ; ARP=AR2, AR0->FR0, AR2->pid_e1_reg1, ARP=AR1
292 ;----------------------------------------------------------------------------------
293 005d _pid_reg1_calc_exit:
294 ;MAR *,AR1 ; can be removed if this condition is met on
295 ; ; every path to this code. (i.e., ARP=AR1 here)
296
297 005d be42 CLRC OVM
298 005e be46 CLRC SXM
299
300 005f 7c06 SBRK #(__pid_reg1_calc_framesize+1)
301 0060 0090 LAR AR0,*-
302 0061 7680 PSHD *
303
304 0062 ef00 RET
305
306
307
No Errors, No Warnings
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