📄 pid_reg1.lst
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C:\TIC2XX\C2000\CGTOOLS\BIN\DSPA.EXE -q -v2xx -gs pid_reg1.asm -o ..\obj\pid_reg1.obj -l ..\temp\pid_reg1.lst
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 1
1 ;=====================================================================================
2 ; File name: PID_REG1.ASM
3 ;
4 ; Originator: Digital Control Systems Group
5 ; Texas Instruments
6 ;
7 ; Description:
8 ; PID Controller
9 ;
10 ;=====================================================================================
11 ; History:
12 ;-------------------------------------------------------------------------------------
13 ; 9-15-2000 Release Rev 1.0
14 ;================================================================================
15 ; Applicability: F240,F241,C242,F243,F24xx. (Peripheral Independent).
16 ;================================================================================
17 ; Routine Name: pid_reg1_calc Type: C Callable
18 ;
19 ; C prototype : void pid_reg1_calc(struct PIDREG1 *p);
20 ;
21 ; The struct object is defined in the header file "pid_reg1.h" as follows:
22 ;
23 ; typedef struct { int pid_ref_reg1; /* Input: Reference input (Q15) */
24 ; int pid_fb_reg1; /* Input: Feedback input (Q15) */
25 ; int Kp_reg1; /* Parameter: Proportional gain (Q15) */
26 ; int Ki_high_reg1; /* Parameter: Integral gain (Q31) */
27 ; int Ki_low_reg1; /* Parameter: Integral gain (Q31) */
28 ; int Kd_reg1; /* Parameter: Derivative gain (Q15) */
29 ; int pid_out_max; /* Parameter: Maximum PID output (Q15) *
30 ; int pid_out_min; /* Parameter: Minimum PID output (Q15) *
31 ; int pid_e1_reg1; /* History: Previous error at time = k-1
32 ; int pid_e2_reg1; /* History: Previous error at time = k-2
33 ; int pid_out_reg1; /* Output: PID output (Q15) */
34 ; int (*calc)(); /* Pointer to calculation function */
35 ; } PIDREG1;
36 ;
37 ; Frame Usage Details:
38 ; step | a | b | c | d
39 ;____________|_____________|______________|______________|_____________
40 ; FR0 | sign_reg1 | | |
41 ; FR1 | abs_e0_reg1 | | |
42 ; FR2 | K0_low_reg1 |tmp2_low_reg1 | |
43 ; FR3 | K0_high_reg1|tmp2_high_reg1| |
44 ; FR4 | K1_reg1 | | |
45 ;
46 ;
47 ;================================================================================
48 .def _pid_reg1_calc
49 ;================================================================================
50 0005 __pid_reg1_calc_framesize .set 0005h
51 ;================================================================================
52 0000 _pid_reg1_calc:
53 ; Assume
54 0000 8aa0 POPD *+ ; Keep return address
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 2
55 0001 80a0 SAR AR0,*+ ; Keep old frame pointer (FP)
56 0002 8180 SAR AR1,* ; Keep old stack pointer (SP)
57 0003 b005 LARK AR0,__pid_reg1_calc_framesize ; Load AR0 with frame size
58 0004 00e8 LAR AR0,*0+,AR0 ; AR0->FP0 (new FP), ARP=AR0
59
60 ;================================================================================
61 0005 7c03 SBRK #3 ; ARP=AR0, AR0->FR0-3 (1st argument)
62 ;----------------------------------------------------------------------------------
63 0006 0280 LAR AR2,* ; ARP=AR0, AR0->pid_ref_reg1, AR2->pid_ref_reg1
64 ;----------------------------------------------------------------------------------
65 0007 7803 ADRK #3 ; ARP=AR0, AR0->FR0, AR2->pid_ref_reg1
66 ;----------------------------------------------------------------------------------
67 0008 8b8a MAR *,AR2 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg1
68 ;----------------------------------------------------------------------------------
69 0009 be47 SETC SXM ; Turn sign extension mode on
70 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg1
71 ;----------------------------------------------------------------------------------
72 000a be43 SETC OVM ; Set overflow mode
73 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg1
74 ;----------------------------------------------------------------------------------
75 000b bf00 SPM 0 ; Reset product mode
76 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg1
77 ;----------------------------------------------------------------------------------
78 000c 10a0 LACC *+ ; ACC = pid_ref_reg1 (Q15)
79 ; ARP=AR2, AR0->FR0, AR2->pid_fb_reg1
80 ;----------------------------------------------------------------------------------
81 000d 30a8 SUB *+,AR0 ; ACC = pid_ref_reg1 - pid_fb_reg1 (Q15)
82 ; ARP=AR2, AR0->FR0, AR2->Kp_reg1, ARP=AR0
83 ;----------------------------------------------------------------------------------
84 000e 90a0 SACL *+ ; FR0=sign_reg1(pid_e0_reg1)=pid_ref_reg1-pid_fb_reg1 (Q15)
85 ; ARP=AR0, AR0->FR1, AR2->Kp_reg1
86 ;----------------------------------------------------------------------------------
87 000f be00 ABS ; ACC = |pid_ref_reg1 - pid_fb_reg1| (Q15)
88 ; ARP=AR0, AR0->FR1, AR2->Kp_reg1
89 ;----------------------------------------------------------------------------------
90 0010 90aa SACL *+,AR2 ; FR1 = abs_e0_reg1 = |pid_ref_reg1 - pid_fb_reg1| (Q15)
91 ; ARP=AR0, AR0->FR2, AR2->Kp_reg, ARP=AR2
92 ;----------------------------------------------------------------------------------
93 0011 7801 ADRK #1 ; ARP=AR2, AR0->FR2, AR2->Ki_high_reg1
94 ;----------------------------------------------------------------------------------
95 0012 6aa0 LACC *+,16 ; ACC high = Ki_high_reg1 (Q31)
96 ; ARP=AR2, AR0->FR2, AR2->Ki_low_reg1
97 ;----------------------------------------------------------------------------------
98 0013 62a0 ADDS *+ ; ACC = Ki_high_reg1 + Ki_low_reg1 (Q31)
99 ; ARP=AR2, AR0->FR2, AR2->Kd_reg1
100 ;----------------------------------------------------------------------------------
101 0014 6180 ADD *,16 ; ACC = Ki + Kd (Q31)
102 ; ARP=AR2, AR0->FR2, AR2->Kd_reg1
103 ;----------------------------------------------------------------------------------
104 0015 7c03 SBRK #3 ; ARP=AR2, AR0->FR2, AR2->Kp_reg1
105 ;----------------------------------------------------------------------------------
106 0016 6188 ADD *,16,AR0 ; ACC = Kp + Ki + Kd (Q31)
107 ; ARP=AR2, AR0->FR2, AR2->Kp_reg1, ARP=AR0
108 ;----------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:13 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
pid_reg1.asm PAGE 3
109 0017 90a0 SACL *+ ; FR2 = K0_low_reg1 = Kp + Ki + Kd (Q31)
110 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
111 ;----------------------------------------------------------------------------------
112 0018 98aa SACH *+,AR2 ; FR3 = K0_high_reg1 = Kp + Ki + Kd (Q31)
113 ; ARP=AR0, AR0->FR4, AR2->Kp_reg1, ARP=AR2
114 ;----------------------------------------------------------------------------------
115 0019 7803 ADRK #3 ; ARP=AR2, AR0->FR4, AR2->Kd_reg1
116 ;----------------------------------------------------------------------------------
117 001a 6a80 LACC *,16 ; ACC = Kd_reg1 (Q15)
118 ; ARP=AR2, AR0->FR4, AR2->Kd_reg1
119 ;----------------------------------------------------------------------------------
120 001b be09 SFL ; ACC = 2*Kd_reg1 (Q15)
121 ; ARP=AR2, AR0->FR4, AR2->Kd_reg1
122 ;----------------------------------------------------------------------------------
123 001c 7c03 SBRK #3 ; ARP=AR2, AR0->FR4, AR2->Kp_reg1
124 ;----------------------------------------------------------------------------------
125 001d 6188 ADD *,16,AR0 ; ACC = 2*Kd_reg1 + Kp_reg1 (Q15)
126 ; ARP=AR2, AR0->FR4, AR2->Kp_reg1, ARP=AR0
127 ;----------------------------------------------------------------------------------
128 001e 9880 SACH * ; FR4 = K1_reg1 = 2*Kd_reg1 + Kp_reg1 (Q15)
129 ; ARP=AR0, AR0->FR4, AR2->Kp_reg1
130 ;----------------------------------------------------------------------------------
131 001f 7c03 SBRK #3 ; ARP=AR0, AR0->FR1, AR2->Kp_reg1
132 ;----------------------------------------------------------------------------------
133 0020 73a0 LT *+ ; TREG = abs_e0_reg1 (Q15)
134 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
135 ;----------------------------------------------------------------------------------
136 0021 5580 MPYU * ; PREG = abs_e0_reg1*K0_low_reg1
137 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
138 ;----------------------------------------------------------------------------------
139 0022 8da0 SPH *+ ; FR2 = tmp2_low_reg1
140 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
141 ;----------------------------------------------------------------------------------
142 0023 5590 MPYU *- ; PREG = abs_e0_reg1*K0_high_reg1
143 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
144 ;----------------------------------------------------------------------------------
145 0024 be03 PAC ; ACC = abs_e0_reg1*K0_high_reg1
146 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
147 ;----------------------------------------------------------------------------------
148 0025 62a0 ADDS *+ ; ACC = abs_e0_reg1*K0_high_reg1 + tmp2_low_reg1
149 ; ARP=AR0, AR0->FR3, AR2->Kp_reg1
150 ;----------------------------------------------------------------------------------
151 0026 9990 SACH *-,1 ; FR3 = tmp2_high_reg1 = abs_e0_reg1*K0 (Q31)
152 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
153 ;----------------------------------------------------------------------------------
154 0027 9180 SACL *,1 ; FR2 = tmp2_low_reg1 = abs_e0_reg1*K0 (Q31)
155 ; ARP=AR0, AR0->FR2, AR2->Kp_reg1
156 ;----------------------------------------------------------------------------------
157 0028 7c02 SBRK #2 ; ARP=AR0, AR0->FR0, AR2->Kp_reg1
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