sincosph.lst

TI的digital motor control lib的源代码。了解TI的编程规范

C:\TIC2XX\C2000\CGTOOLS\BIN\DSPA.EXE -q -v2xx -gs sincosph.asm -o ..\obj\sincosph.obj -l ..\temp\sincosph.lst 

TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:16 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
sincosph.asm                                                         PAGE    1

       1            ;=====================================================================================
       2            ; File name:        SINCOSPH.ASM                      
       3            ;                    
       4            ; Originator:   Digital Control Systems Group
       5            ;                       Texas Instruments
       6            ;
       7            ; Description:                                 
       8            ; Sine-Cosine generation with phase/magitude/frequency control
       9            ;=====================================================================================
      10            ; History:
      11            ;-------------------------------------------------------------------------------------
      12            ; 9-15-2000     Release Rev 1.0
      13            ;================================================================================
      14            ; Applicability: F240,F241,C242,F243,F24xx.  (Peripheral Independent).
      15            ;================================================================================
      16            ; Routine Name: sincosph_calc                                                       Type: C Callable
      17            ;  
      18            ;  C prototype : void sincosph_calc(struct SINCOSPH *p);
      19            ;
      20            ;        The struct object is defined in the header file "sincosph.h" as follows:
      21            ;
      22            ; typedef struct { int  phase_cs;               /* Input: Phase shift in degree (Q0) */ 
      23            ;                                  int  freq_cs;                /* Input: Frequency (Q15) */            
      24            ;                                  int  gain_cs;                /* Input: Magnitude (Q15) */                    
      25            ;                                  int  sg2_freq_max;   /* Parameter: Maximum step angle (Q0) */
      26            ;                                  int  ALPHA_a1;               /* Variable: Incremental angle (Q0) */  
      27            ;                                  int  sine_a1;                /* Output: Sinusoidal output 1 (Q15) */         
      28            ;                                  int  sine_a2;                /* Output: Sinusoidal output 2 (Q15) */
      29            ;                                  int  (*calc)();              /* Pointer to calculation function */ 
      30            ;                                } SINCOSPH;                
      31            ;        
      32            ;                        
      33            ;        Frame Usage Details:
      34            ;     step  |   a   |      b      |    c    |  d   |   e     |
      35            ;___________|_______|_____________|_________|______|_________|
      36            ;     FR0   |  GPR  | STEP_ANGLE2 | ENTRY13 | GPRC | ENTRY13 |  
      37            ;     FR1   | phase |             |         |      |         |
      38            ;
      39            ;================================================================================
      40                            .def        _sincosph_calc    
      41                            .ref            SINTAB_360          ; Sine look-up table (256 entries)  
      42            ;================================================================================
      43      0002  __sincosph_calc_framesize       .set    0002h
      44            ;================================================================================
      45 0000       _sincosph_calc:
      46                                                                                                                    ; Assume
      47 0000 8aa0          POPD    *+                                                                      ; Keep return address
      48 0001 80a0          SAR     AR0,*+                                                          ; Keep old frame pointer (FP)
      49 0002 8180          SAR     AR1,*                                                           ; Keep old stack pointer (SP)
      50 0003 b002          LARK    AR0,__sincosph_calc_framesize           ; Load AR0 with frame size      
      51 0004 00e8          LAR     AR0,*0+,AR0                                                     ; AR0->FP0 (new FP), ARP=AR0
      52            
      53            ;================================================================================
      54 0005 7c03                  SBRK    #3              ; ARP=AR0, AR0->FR0-3 (1st argument)            
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:16 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
sincosph.asm                                                         PAGE    2

      55            ;----------------------------------------------------------------------------------
      56 0006 0280                  LAR             AR2,*   ; ARP=AR0, AR0->phase_cs, AR2->phase_cs                 
      57            ;----------------------------------------------------------------------------------
      58 0007 7803                  ADRK    #3              ; ARP=AR0, AR0->FR0, AR2->phase_cs 
      59            ;----------------------------------------------------------------------------------
      60 0008 be46                  CLRC    SXM             ; Turn sign extension mode off
      61                                                            ; ARP=AR0, AR0->FR0, AR2->phase_cs
      62            ;----------------------------------------------------------------------------------
      63 0009 be43                  SETC    OVM             ; Set overflow mode
      64                                                            ; ARP=AR0, AR0->FR0, AR2->phase_cs
      65            ;----------------------------------------------------------------------------------
      66 000a bf00                  SPM     0       ; Reset product mode
      67                                                    ; ARP=AR0, AR0->FR0, AR2->phase_cs 
      68            ;----------------------------------------------------------------------------------
      69 000b ae80                  SPLK    #0B6h,* ; FR0 = 0B6h
         000c 00b6  
      70                                                            ; ARP=AR0, AR0->FR0, AR2->phase_cs
      71            ;----------------------------------------------------------------------------------
      72 000d 73aa                  LT              *+,AR2  ; TREG = FR0 = 0B6h
      73                                                            ; ARP=AR0, AR0->FR1, AR2->phase_cs, ARP=AR2
      74            ;----------------------------------------------------------------------------------
      75 000e 54a8                  MPY             *+,AR0  ; PREG = 0B6h*phase_cs
      76                                                            ; ARP=AR2, AR0->FR1, AR2->freq_cs, ARP=AR0      
      77            ;----------------------------------------------------------------------------------
      78 000f be03                  PAC                             ; ACC = 0B6h*phase_cs
      79                                                            ; ARP=AR0, AR0->FR1, AR2->freq_cs       
      80            ;----------------------------------------------------------------------------------
      81 0010 909a          SACL    *-,AR2  ; FR1 = phase = 0B6h*phase_cs
      82                                                    ; ARP=AR0, AR0->FR0, AR2->freq_cs, ARP=AR2 
      83            ;----------------------------------------------------------------------------------
      84 0011 7380                  LT              *               ; TREG = freq_cs (Q15)
      85                                                            ; ARP=AR2, AR0->FR0, AR2->freq_cs
      86            ;----------------------------------------------------------------------------------
      87 0012 7802                  ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->sg2_freq_max
      88            ;----------------------------------------------------------------------------------
      89 0013 54a8                  MPY             *+,AR0  ; PREG = freq_cs*sg2_freq_max  (Q15)
      90                                                            ; ARP=AR2, AR0->FR0, AR2->ALPHA_a1, ARP=AR0
      91            ;----------------------------------------------------------------------------------
      92 0014 be03          PAC                             ; ACC = freq_cs*sg2_freq_max  (Q15)
      93                                                            ; ARP=AR0, AR0->FR0, AR2->ALPHA_a1
      94            ;----------------------------------------------------------------------------------
      95 0015 998a                  SACH    *,1,AR2 ; FR0 = STEP_ANGLE2
      96                                                            ; ARP=AR0, AR0->FR0, AR2->ALPHA_a1, ARP=AR2     
      97            ;----------------------------------------------------------------------------------
      98 0016       SG_a1                   ; ARP=AR2, AR0->FR0, AR2->ALPHA_a1
      99            ;----------------------------------------------------------------------------------
     100 0016 1088          LACC    *,AR0   ; ACC = ALPHA_a1