📄 svgen_dq.lst
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457 ;--------------------------------------------------------------------------------
458
459 009e 8ba0 MAR *+ ; AR2++. Now AR2 -> tb
460 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
461 ;--------------------------------------------------------------------------------
462 009f 90ab SACL *+,AR3 ; Store tb
463 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
464 ;--------------------------------------------------------------------------------
465 00a0 20aa ADD *+,AR2 ; ACC = tb + t1.
466 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
467 ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 10
468 00a1 908b SACL *,AR3 ; Store tc = tb + t1.
469 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
470 ;--------------------------------------------------------------------------------
471 00a2 208a ADD *,AR2 ; ACC = tc + t2.
472 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
473 ;--------------------------------------------------------------------------------
474 00a3 7c02 SBRK #2 ; Point AR2 to ta.
475 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
476 ;--------------------------------------------------------------------------------
477 00a4 90a0 SACL *+ ; Store ta.
478 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
479 ;--------------------------------------------------------------------------------
480 00a5 7980 B SV_POST_PROCESS
00a6 00bc'
481 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
482 ;--------------------------------------------------------------------------------
483 ; Sector Subroutine #6. On arrival :
484 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
485 ;--------------------------------------------------------------------------------
486 00a7 7c01 SECTOR_SR6: SBRK #1 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
487
488 00a8 10ab LACC *+,AR3 ; ACC = Y
489 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
490 ;--------------------------------------------------------------------------------
491 00a9 be02 NEG ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
492 ;--------------------------------------------------------------------------------
493 00aa 90a8 SACL *+,AR0 ; Store t1 = -Y. ( FR3 = t1.)
494 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
495 ;--------------------------------------------------------------------------------
496 00ab 109b LACC *-,AR3 ; ACC = Z.
497 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
498 ;--------------------------------------------------------------------------------
499 00ac be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
500 ;--------------------------------------------------------------------------------
501 00ad 9090 SACL *- ; Store t2 = -Z. ( FR4 = t2.)
502 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
503 ;--------------------------------------------------------------------------------
504 00ae bf80 LACC #7fffh ; ACCL= 1 (Q15).
00af 7fff
505 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
506 ;--------------------------------------------------------------------------------
507 00b0 30a0 SUB *+ ; ACC = 1-t1.
508 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
509 ;--------------------------------------------------------------------------------
510 00b1 309a SUB *-,AR2 ; ACC = 1-t1=t2.
511 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
512 ;--------------------------------------------------------------------------------
513 00b2 be0a SFR ; ACC = (1-t1=t2)/2.
514 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
515 ;--------------------------------------------------------------------------------
516 00b3 7802 ADRK #2 ; AR2+=2. Now AR2 -> tc
517 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
518 ;--------------------------------------------------------------------------------
519 00b4 908b SACL *,AR3 ; Store tc
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 11
520 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
521 ;--------------------------------------------------------------------------------
522 00b5 20aa ADD *+,AR2 ; ACC = tc + t1.
523 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
524 ;--------------------------------------------------------------------------------
525 00b6 7c02 SBRK #2 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
526 ;--------------------------------------------------------------------------------
527 00b7 90ab SACL *+,AR3 ; Store ta = tc + t1.
528 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
529 ;--------------------------------------------------------------------------------
530 00b8 208a ADD *,AR2 ; ACC = ta + t2.
531 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
532 ;--------------------------------------------------------------------------------
533 00b9 9080 SACL * ; Store tb.
534 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
535 ;--------------------------------------------------------------------------------
536 00ba 7980 B SV_POST_PROCESS
00bb 00bc'
537 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
538 ;--------------------------------------------------------------------------------
539
540
541 00bc SV_POST_PROCESS: ; On arrival: ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
542
543 ; Multiply tb by 2 and subtract offset = 1/2. for ta,tb,tc.
544 ;-------------------------------------------------------------------------------
545 00bc 8b90 MAR *- ; AR2--
546 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
547 ;-------------------------------------------------------------------------------
548 00bd 1080 LACC * ; Get ta
549 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
550 ;-------------------------------------------------------------------------------
551 00be bfa0 SUB #3FFFh ; Subtract offset.
00bf 3fff
552 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
553 ;-------------------------------------------------------------------------------
554 00c0 91a0 SACL *+,1 ; Store (ta-0.5)*2
555 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
556 ;-------------------------------------------------------------------------------
557 00c1 1080 LACC * ; Get tb
558 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
559 ;-------------------------------------------------------------------------------
560 00c2 bfa0 SUB #3FFFh ; Subtract offset.
00c3 3fff
561 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
562 ;-------------------------------------------------------------------------------
563 00c4 91a0 SACL *+,1 ; Store (tb-0.5)*2
564 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
565 ;-------------------------------------------------------------------------------
566 00c5 1080 LACC * ; Get tc
567 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
568 ;-------------------------------------------------------------------------------
569 00c6 bfa0 SUB #3FFFh ; Subtract offset.
00c7 3fff
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 12
570 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
571 ;-------------------------------------------------------------------------------
572 00c8 9189 SACL *,1,AR1 ; Store (tc-0.5)*2
573 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
574 ;-------------------------------------------------------------------------------
575 00c9 __svgendq_exit:
576 ;;;;MAR *,AR1 ; can be removed if this condition is met on
577 ;;;; ; every path to this code.
578
579
580 00c9 bf00 SPM 0
581 00ca be42 CLRC OVM
582
583
584 00cb 7c06 SBRK #(__svgendq_framesize+1)
585 00cc 0090 LAR AR0,*-
586 00cd 7680 PSHD *
587 00ce ef00 RET
588
589 ;-------------------------------------------------------------------------------
590 ;SVPWM Sector routine jump table (Used to ref with BACC instruction
591 ;-------------------------------------------------------------------------------
592 00cf SECTOR_TABLE_BASE:
593
594 00cf 0000 SR0 .word 0
595 00d0 0048' SR1 .word SECTOR_SR1
596 00d1 005a' SR2 .word SECTOR_SR2
597 00d2 006d' SR3 .word SECTOR_SR3
598 00d3 007f' SR4 .word SECTOR_SR4
599 00d4 0093' SR5 .word SECTOR_SR5
600 00d5 00a7' SR6 .word SECTOR_SR6
601 00d6 0000 SR7 .word 0
602
603
No Errors, No Warnings
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