svgen_dq.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     304                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     305            ;--------------------------------------------------------------------------------
     306 0066 20aa                  ADD     *+,AR2  ; ACC = ta + t1.
     307                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     308            ;--------------------------------------------------------------------------------
     309 0067 7802                  ADRK    #2      ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
     310            ;--------------------------------------------------------------------------------
     311 0068 909b                  SACL    *-,AR3  ; Store tc = ta + t1.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    7

     312                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
     313            ;--------------------------------------------------------------------------------
     314 0069 208a                  ADD     *,AR2   ; ACC = tc + t2.
     315                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     316            ;--------------------------------------------------------------------------------
     317 006a 9080                  SACL    *       ; Store tb.
     318                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     319            ;--------------------------------------------------------------------------------
     320 006b 7980                  B       SV_POST_PROCESS
         006c 00bc' 
     321            ;--------------------------------------------------------------------------------
     322            ; Sector Subroutine #3. On arrival : 
     323            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     324            ;--------------------------------------------------------------------------------
     325 006d 109b  SECTOR_SR3:     LACC    *-,AR3  ; ACC = Z
     326                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     327            ;--------------------------------------------------------------------------------
     328 006e be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     329            ;--------------------------------------------------------------------------------
     330 006f 90a8                  SACL    *+,AR0  ; Store t1 = -Z. ( FR3 = t1.)
     331                                            ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     332            ;--------------------------------------------------------------------------------
     333 0070 8b90                  MAR     *-      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
     334            ;--------------------------------------------------------------------------------
     335            
     336 0071 10ab                  LACC    *+,AR3  ; ACC = X.
     337                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     338            ;--------------------------------------------------------------------------------
     339 0072 9090                  SACL    *-      ; Store t2 = X. ( FR4 = t2.)
     340                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     341            ;--------------------------------------------------------------------------------
     342 0073 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         0074 7fff  
     343                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     344            ;--------------------------------------------------------------------------------
     345 0075 30a0                  SUB     *+      ; ACC = 1-t1.
     346                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     347            ;--------------------------------------------------------------------------------
     348 0076 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     349                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     350            ;--------------------------------------------------------------------------------
     351 0077 be0a                  SFR             ; ACC = (1-t1=t2)/2.
     352                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     353            ;--------------------------------------------------------------------------------
     354 0078 90ab                  SACL    *+,AR3  ; Store ta
     355                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
     356            ;--------------------------------------------------------------------------------
     357 0079 20aa                  ADD     *+,AR2  ; ACC = ta + t1
     358                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     359            ;--------------------------------------------------------------------------------
     360 007a 90ab                  SACL    *+,AR3   ; Store tb = ta + t1.
     361                                            ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
     362            ;--------------------------------------------------------------------------------
     363 007b 208a                  ADD     *,AR2   ; ACC = tb + t2.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    8

     364                                            ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
     365            ;--------------------------------------------------------------------------------
     366 007c 9090                  SACL    *-      ; Store tc.
     367                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     368            ;--------------------------------------------------------------------------------
     369 007d 7980                  B       SV_POST_PROCESS
         007e 00bc' 
     370                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     371            ;--------------------------------------------------------------------------------
     372            
     373            ;--------------------------------------------------------------------------------
     374            ; Sector Subroutine #4. On arrival : 
     375            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     376            ;--------------------------------------------------------------------------------
     377 007f 7c02  SECTOR_SR4:     SBRK    #2      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
     378            ;--------------------------------------------------------------------------------
     379 0080 10ab                  LACC    *+,AR3  ; ACC = X
     380                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     381            ;--------------------------------------------------------------------------------
     382 0081 be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     383            ;--------------------------------------------------------------------------------
     384 0082 90a8                  SACL    *+,AR0  ; Store t1 = -X. ( FR3 = t1.)
     385                                            ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     386            ;--------------------------------------------------------------------------------
     387 0083 8ba0                  MAR     *+      ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
     388            ;--------------------------------------------------------------------------------
     389 0084 109b                  LACC    *-,AR3  ; ACC = Z.
     390                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     391            ;--------------------------------------------------------------------------------
     392 0085 9090                  SACL    *-      ; Store t2 = Y. ( FR4 = t2.)
     393                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     394            ;--------------------------------------------------------------------------------
     395 0086 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         0087 7fff  
     396                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     397            ;--------------------------------------------------------------------------------
     398 0088 30a0                  SUB     *+      ; ACC = 1-t1.
     399                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     400            ;--------------------------------------------------------------------------------
     401 0089 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     402                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     403            ;--------------------------------------------------------------------------------
     404 008a be0a                  SFR             ; ACC = (1-t1=t2)/2.
     405                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     406            ;--------------------------------------------------------------------------------
     407 008b 7802                  ADRK    #2      ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
     408            ;--------------------------------------------------------------------------------
     409 008c 909b                  SACL    *-,AR3  ; Store tc
     410                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
     411            ;--------------------------------------------------------------------------------
     412 008d 20aa                  ADD     *+,AR2  ; ACC = tc + t1
     413                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     414            ;--------------------------------------------------------------------------------
     415 008e 909b                  SACL    *-,AR3  ; Store tb = tc + t1.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    9

     416                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     417            ;--------------------------------------------------------------------------------
     418 008f 208a                  ADD     *,AR2   ; ACC = tb + t2.
     419                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     420            ;--------------------------------------------------------------------------------
     421 0090 90a0                  SACL    *+      ; Store ta.
     422                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     423            ;--------------------------------------------------------------------------------
     424 0091 7980                  B       SV_POST_PROCESS
         0092 00bc' 
     425                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     426            ;--------------------------------------------------------------------------------
     427            ; Sector Subroutine #5. On arrival : 
     428            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     429            ;--------------------------------------------------------------------------------
     430 0093 7c02  SECTOR_SR5:     SBRK    #2      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
     431            
     432 0094 10ab                  LACC    *+,AR3  ; ACC = X
     433                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     434            ;--------------------------------------------------------------------------------
     435 0095 90a8                  SACL    *+,AR0  ; Store t1 = X. ( FR3 = t1.)
     436                              ;      ^      ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     437            ;--------------------------------------------------------------------------------
     438 0096 108b                  LACC    *,AR3   ; ACC = Y.
     439                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     440            ;--------------------------------------------------------------------------------
     441 0097 be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     442            ;--------------------------------------------------------------------------------
     443 0098 9090                  SACL    *-      ; Store t2 = -Y. ( FR4 = t2.)
     444                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     445            ;--------------------------------------------------------------------------------
     446 0099 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         009a 7fff  
     447                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     448            ;--------------------------------------------------------------------------------
     449 009b 30a0                  SUB     *+      ; ACC = 1-t1.
     450                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     451            ;--------------------------------------------------------------------------------
     452 009c 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     453                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     454            ;--------------------------------------------------------------------------------
     455 009d be0a                  SFR             ; ACC = (1-t1=t2)/2.
     456                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.