svgen_dq.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     152            
     153 002d 1080  vref2_neg:      LACC    *       ; Load va
     154                                            ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
     155            ;--------------------------------------------------------------------------------
     156 002e e3cc                  BCND    vref1_neg,LEQ
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    4

         002f 0035' 
     157                                            ; If vb<0 then do not set bit 1 of sector.
     158                                            ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
     159            ;--------------------------------------------------------------------------------
     160 0030 8b8b                  MAR     *,AR3   ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
     161            ;--------------------------------------------------------------------------------
     162 0031 1080                  LACC    *       ; Get sector code.
     163                                            ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
     164            ;--------------------------------------------------------------------------------
     165 0032 bfc0                  OR      #1      ; Set bit 0.
         0033 0001  
     166                                            ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
     167            ;--------------------------------------------------------------------------------
     168 0034 9088                  SACL    *,AR0   ; Store sector code
     169                                            ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
     170 0035       vref1_neg:                      
     171            
     172            ;--------------------------------------------------------------------------------
     173 0035 8b8a                  MAR     *,AR2   ; ARP=AR2. AR0->FR0 AR2->q AR3->FR3
     174            ;--------------------------------------------------------------------------------
     175 0036 1098                  LACC    *-,AR0  ; ACC = q.
     176                                            ; ARP=AR0. AR0->FR0 AR2->d AR3->FR3
     177            ;--------------------------------------------------------------------------------
     178 0037 90a0                  SACL    *+      ; Store FR0=X=q.
     179                                            ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
     180            ;--------------------------------------------------------------------------------
     181 0038 ae80                  SPLK    #28377,* ;FR1 = sqrt(3) / 2.
         0039 6ed9  
     182                                            ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
     183            ;--------------------------------------------------------------------------------
     184 003a 738a                  LT      *,AR2   ; TREG = sqrt(3) / 2.
     185                                            ; ARP=AR2. AR0->FR1 AR2->d AR3->FR3
     186            ;--------------------------------------------------------------------------------
     187 003b 54a0                  MPY     *+      ; PREG = d * sqrt(3) / 2.
     188                                            ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
     189            ;--------------------------------------------------------------------------------
     190 003c be03                  PAC             ; ACC = d * sqrt(3) / 2.
     191                                            ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
     192            ;--------------------------------------------------------------------------------
     193 003d 2f88                  ADD     *,15,AR0 ; ACCH= q/2 + d * sqrt(3) / 2.
     194                                            ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
     195            ;--------------------------------------------------------------------------------
     196 003e 98aa                  SACH    *+,AR2  ; Store FR1 = Y = q/2 + d * sqrt(3) / 2.
     197                                            ; ARP=AR2. AR0->FR2 AR2->q AR3->FR3
     198            ;--------------------------------------------------------------------------------
     199 003f 1fa8                  LACC    *+,15,AR0 ; ACCH = q/2.
     200                                            ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     201            ;--------------------------------------------------------------------------------
     202 0040 be05                  SPAC            ; ACCH = q/2 - d * sqrt(3) / 2.
     203                                            ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     204            ;--------------------------------------------------------------------------------
     205 0041 988b                  SACH    *,AR3   ; Store FR2 = Z = q/2 - d * sqrt(3) / 2.
     206                                            ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
     207            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    5

     208 0042 10a0                  LACC    *+      ; Load sector #.
     209                                            ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
     210            ;--------------------------------------------------------------------------------
     211 0043 bf90                  ADD     #SECTOR_TABLE_BASE
         0044 00cf' 
     212            ;--------------------------------------------------------------------------------
     213 0045 a680                  TBLR    *       ; FR3 = Sector subroutine address.
     214                                            ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
     215            ;--------------------------------------------------------------------------------
     216 0046 1088                  LACC    *,AR0   ; ACC = Sector subroutine address.
     217                                            ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     218            ;--------------------------------------------------------------------------------
     219 0047 be20                  BACC            ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     220            ;--------------------------------------------------------------------------------
     221            ; Sector Subroutine #1. On arrival : 
     222            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     223            ;--------------------------------------------------------------------------------
     224 0048 109b  SECTOR_SR1:     LACC    *-,AR3  ; ACC = Z
     225                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     226            ;--------------------------------------------------------------------------------
     227 0049 90a8                  SACL    *+,AR0  ; Store t1 = Z. ( FR3 = t1.)
     228                                            ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     229            ;--------------------------------------------------------------------------------
     230 004a 108b                  LACC    *,AR3   ; ACC = Y.
     231                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     232            ;--------------------------------------------------------------------------------
     233 004b 9090                  SACL    *-      ; Store t2 = Y. ( FR4 = t2.)
     234                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     235            ;--------------------------------------------------------------------------------
     236 004c bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         004d 7fff  
     237                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     238            ;--------------------------------------------------------------------------------
     239 004e 30a0                  SUB     *+      ; ACC = 1-t1.
     240                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     241            ;--------------------------------------------------------------------------------
     242 004f 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     243                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     244            ;--------------------------------------------------------------------------------
     245 0050 be0a                  SFR             ; ACC = (1-t1=t2)/2.
     246                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     247            ;--------------------------------------------------------------------------------
     248 0051 8ba0                  MAR     *+      ; AR2++. Now AR2 -> tb
     249                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
     250            ;--------------------------------------------------------------------------------
     251 0052 909b                  SACL    *-,AR3  ; Store tb
     252                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     253            ;--------------------------------------------------------------------------------
     254 0053 20aa                  ADD     *+,AR2  ; ACC = tb + t1.
     255                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     256            ;--------------------------------------------------------------------------------
     257 0054 908b                  SACL    *,AR3   ; Store ta = tb + t1.
     258                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     259            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:06 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    6

     260 0055 208a                  ADD     *,AR2   ; ACC = tb + t2.
     261                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     262            ;--------------------------------------------------------------------------------
     263 0056 7802                  ADRK    #2      ; Point AR2 to tc.
     264                                            ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
     265            ;--------------------------------------------------------------------------------
     266 0057 9090                  SACL    *-      ; Store tc.
     267                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     268            ;--------------------------------------------------------------------------------
     269 0058 7980                  B       SV_POST_PROCESS
         0059 00bc' 
     270                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     271            ;--------------------------------------------------------------------------------
     272            ; Sector Subroutine #2. On arrival : 
     273            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     274            ;--------------------------------------------------------------------------------
     275 005a 8b90  SECTOR_SR2:     MAR     *-      ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
     276            ;--------------------------------------------------------------------------------
     277 005b 109b                  LACC    *-,AR3  ; ACC = Y
     278                                            ; ARP=AR3. AR0->FR0 AR2->ta AR3->FR3.
     279            ;--------------------------------------------------------------------------------
     280 005c 90a8                  SACL    *+,AR0  ; Store t1 = Y. ( FR3 = t1.)
     281                                            ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
     282            ;--------------------------------------------------------------------------------
     283 005d 10ab                  LACC    *+,AR3  ; ACC = X.
     284                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     285            ;--------------------------------------------------------------------------------
     286 005e be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     287            ;--------------------------------------------------------------------------------
     288 005f 9090                  SACL    *-      ; Store t2 = -X. ( FR4 = t2.)
     289                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     290            ;--------------------------------------------------------------------------------
     291 0060 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         0061 7fff  
     292                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     293            ;--------------------------------------------------------------------------------
     294 0062 30a0                  SUB     *+      ; ACC = 1-t1.
     295                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     296            ;--------------------------------------------------------------------------------
     297 0063 309a                  SUB     *-,AR2  ; ACC = 1-t1-t2.
     298                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     299            ;--------------------------------------------------------------------------------
     300 0064 be0a                  SFR             ; ACC = (1-t1-t2)/2.
     301                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     302            ;--------------------------------------------------------------------------------
     303 0065 908b                  SACL    *,AR3  ; Store ta