📄 svgen_dq.lst
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C:\TIC2XX\C2000\CGTOOLS\BIN\DSPA.EXE -q -v2xx -gs svgen_dq.asm -o ..\obj\svgen_dq.obj -l ..\temp\svgen_dq.lst
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 1
1 ;=====================================================================================
2 ; File name: SVGEN_DQ.ASM
3 ;
4 ; Originator: Digital Control Systems Group
5 ; Texas Instruments
6 ;
7 ; Description:
8 ; This file contains source for Space vector modulation dq -> SV(a,b,c).
9 ;=====================================================================================
10 ; History:
11 ;-------------------------------------------------------------------------------------
12 ; 9-15-2000 Release Rev 1.0
13 ;================================================================================
14 ; Applicability: F240,F241,C242,F243,F24xx. (Peripheral Independant).
15 ;================================================================================
16 ; Routine Name: svgendq Routine Type: C Callable
17 ;
18 ; Description:
19 ;
20 ; C prototype : int svgendq(struct SVGENDQ *p);
21 ;
22 ; The struct is defined as follows:
23 ;
24 ; typedef struct SVGENDQ { int d,q,ta,tb,tc ; };
25 ;
26 ; Frame Usage Details:
27 ; | a | b | c | d
28 ;____________|_____________|_______________|____________|_____________
29 ; FR0 | va | X | X | X
30 ; FR1 | vb | Y | Y | Y
31 ; FR2 | vc | Z | Z | Z
32 ; FR3 | sector | sector | sr_address | t1
33 ; FR4 | | | | t2
34
35
36
37 ;================================================================================
38 .def _svgendq_calc
39 ;================================================================================
40 0005 __svgendq_framesize .set 0005h
41 ;================================================================================
42 0000 _svgendq_calc:
43 0000 8aa0 POPD *+
44 0001 80a0 SAR AR0,*+
45 0002 8180 SAR AR1,*
46 0003 b005 LARK AR0,__svgendq_framesize
47 0004 00e8 LAR AR0,*0+,AR0
48
49 ;================================================================================
50 0005 7c03 SBRK #3 ; Point AR0 to the first argument.
51 ;--------------------------------------------------------------------------------
52 0006 0280 LAR AR2,*
53 ; get the argument in AR2.
54 ; ARP=AR0. AR0->([FR0-3]=Argument 1) and AR2->d
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 2
55 0007 7803 ADRK #3 ; ARP=AR0. AR0->FR0 and AR2->d
56
57 0008 8b8a MAR *,AR2 ; ARP=AR2. AR0->FR0 and AR2->d
58 ;--------------------------------------------------------------------------------
59 0009 bf01 SPM 1 ; Set product shift mode to one.
60 ; ARP=AR2. AR0->FR0 and AR2->d
61 ;--------------------------------------------------------------------------------
62 000a be47 SETC SXM ; Turn sign extension mode on.
63 ; ARP=AR2. AR0->FR0 and AR2->d
64
65 ;--------------------------------------------------------------------------------
66 000b 7801 ADRK #1 ; ARP=AR2. AR0->FR0 and AR2->q
67 ;--------------------------------------------------------------------------------
68 000c 1098 LACC *-,AR0 ; Load q.
69 ; ARP=AR0. AR0->FR0 and AR2->d
70 ;--------------------------------------------------------------------------------
71 000d 90a0 SACL *+ ; Store va=q
72 ; ARP=AR0. AR0->FR1 and AR2->d
73 ;--------------------------------------------------------------------------------
74 000e ae80 SPLK #28377,*
000f 6ed9
75 ; FR1 = 0.5*qrt3.
76 ; ARP=AR0. AR0->FR1 and AR2->d
77 ;--------------------------------------------------------------------------------
78 0010 738a LT *,AR2 ; TREG = 0.5*qrt3.
79 ; ARP=AR2. AR0->FR1 and AR2->d
80 ;--------------------------------------------------------------------------------
81 0011 54a0 MPY *+ ; PREG = d * 0.5sqrt(3).
82 ; ARP=AR2. AR0->FR1 and AR2->q
83 ;--------------------------------------------------------------------------------
84 0012 b900 ZAC ; ACCH:ACCL=0.
85 ; ARP=AR2. AR0->FR1 and AR2->q
86 ;--------------------------------------------------------------------------------
87 0013 3f88 SUB *,15,AR0 ;ACC = -q/2
88 ; ARP=AR0. AR0->FR1 and AR2->q
89 ;--------------------------------------------------------------------------------
90 0014 be04 APAC ; ACC = -q/2 + d * 0.5sqrt(3)
91 ; ARP=AR0. AR0->FR1 and AR2->q
92 ;--------------------------------------------------------------------------------
93 0015 98a0 SACH *+ ; Store vb.
94 ; ARP=AR0. AR0->FR2 and AR2->q
95 ;--------------------------------------------------------------------------------
96 0016 be05 SPAC ; ACC = -q/2
97 ; ARP=AR0. AR0->FR2 and AR2->q
98 ;--------------------------------------------------------------------------------
99 0017 be05 SPAC ; ACC = -q/2 - (d * 0.5sqrt(3))
100 ; ARP=AR0. AR0->FR2 and AR2->q
101 ;--------------------------------------------------------------------------------
102 0018 98a0 SACH *+ ; Store vc.
103 ; ARP=AR0. AR0->FR3 and AR2->q
104 ;--------------------------------------------------------------------------------
105 0019 8080 SAR AR0,* ; FR3 = AR0 = &FR3.
106 ; ARP=AR0. AR0->FR3 and AR2->q
107 ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:06 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 3
108 001a 039b LAR AR3,*-,AR3
109 ; AR3 = FR3 = &FR3.
110 ; i.e. now AR3 points to FR3.
111 ; ARP=AR3. AR0->FR2 AR2->q AR3->FR3
112 ;--------------------------------------------------------------------------------
113 001b ae88 SPLK #0,*,AR0
001c 0000
114 ; Store sector = FR3 = 0
115 ; ARP=AR0. AR0->FR2 AR2->q AR3->FR3
116 ;--------------------------------------------------------------------------------
117 001d 1090 LACC *- ; Load vc.
118 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
119 ;--------------------------------------------------------------------------------
120 001e e3cc BCND vref3_neg,LEQ
001f 0025'
121 ; If vc<0 then do not set bit 2 of sector.
122 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
123 ;--------------------------------------------------------------------------------
124 0020 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
125 ;--------------------------------------------------------------------------------
126 0021 1080 LACC * ; Get sector code.
127 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
128 ;--------------------------------------------------------------------------------
129 0022 bfc0 OR #4 ; Set bit 2.
0023 0004
130 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
131 ;--------------------------------------------------------------------------------
132 0024 9088 SACL *,AR0 ; Store sector code
133 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
134 ;--------------------------------------------------------------------------------
135 0025 1090 vref3_neg: LACC *- ; Load vb
136 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
137 ;--------------------------------------------------------------------------------
138 0026 e3cc BCND vref2_neg,LEQ
0027 002d'
139 ; If vb<0 then do not set bit 1 of sector.
140 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
141 ;--------------------------------------------------------------------------------
142 0028 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
143 ;--------------------------------------------------------------------------------
144 0029 1080 LACC * ; Get sector code.
145 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
146 ;--------------------------------------------------------------------------------
147 002a bfc0 OR #2 ; Set bit 1.
002b 0002
148 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
149 ;--------------------------------------------------------------------------------
150 002c 9088 SACL *,AR0 ; Store sector code
151 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
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