trap_gen.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     220            ;----------------------------------------------------------------------------------
     221 004a 7c08                  SBRK    #8              ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr
     222            ;----------------------------------------------------------------------------------
     223 004b 7980          B       RESET_DELAY  ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr
         004c 006d' 
     224            ;----------------------------------------------------------------------------------
     225 004d       MAX_TRAP                                ; ARP=AR2, AR0->FR1, AR2->trap_timer 
     226            ;----------------------------------------------------------------------------------
     227 004d 7802                  ADRK    #2              ; ARP=AR2, AR0->FR1, AR2->trap_max_tmp
     228            ;----------------------------------------------------------------------------------
     229 004e 6a80          LACC    *,16    ; ACC = trap_max_tmp  (Q15)
     230                                                    ; ARP=AR2, AR0->FR1, AR2->trap_max_tmp
     231            ;----------------------------------------------------------------------------------
     232 004f 7805          ADRK    #5              ; ARP=AR2, AR0->FR1, AR2->trap_out
     233            ;----------------------------------------------------------------------------------
     234 0050 9890                  SACH    *-              ; trap_out = trap_max_tmp  (Q15)
     235                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     236            ;----------------------------------------------------------------------------------
     237 0051 9080                  SACL    *               ; trap_out = trap_max_tmp  (Q15)
     238                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     239            ;----------------------------------------------------------------------------------
     240 0052 7c08                  SBRK    #8              ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr 
     241            ;----------------------------------------------------------------------------------
     242 0053 7980          B       RESET_DELAY  ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr
         0054 006d' 
     243            ;----------------------------------------------------------------------------------
     244 0055       DECREASE_TRAP           ; ARP=AR2, AR0->FR1, AR2->trap_timer
     245            ;----------------------------------------------------------------------------------
     246 0055 7802          ADRK    #2              ; ARP=AR2, AR0->FR1, AR2->trap_max_tmp  
     247            ;----------------------------------------------------------------------------------
     248 0056 1f80          LACC    *,15    ; ACC = trap_max_tmp (Q14)
     249                                                    ; ARP=AR2, AR0->FR1, AR2->trap_max_tmp  
     250            ;----------------------------------------------------------------------------------
     251 0057 7803          ADRK    #3              ; ARP=AR2, AR0->FR1, AR2->trap_min_tmp 
     252            ;----------------------------------------------------------------------------------
     253 0058 3fa8                  SUB             *+,15,AR0       ; ACC = trap_max_tmp - trap_min_tmp (Q14)
     254                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo, ARP=AR0  
     255            ;----------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:22 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
trap_gen.asm                                                         PAGE    6

     256 0059 9890          SACH    *-              ; FR1 = trap_tmp1 = trap_max_tmp - trap_min_tmp (Q14)
     257                                                    ; ARP=AR0, AR0->FR0, AR2->trap_out_lo  
     258            ;----------------------------------------------------------------------------------
     259 005a 73a0                  LT              *+              ; TREG = FR0 = trap_8192inv = 1/8192   (Q15)
     260                                                            ; ARP=AR0, AR0->FR1, AR2->trap_out_lo  
     261            ;----------------------------------------------------------------------------------
     262 005b 548a                  MPY             *,AR2   ; PREG = (1/8192)*(trap_max_tmp-trap_min_tmp)  (Q29)
     263                                                            ; ARP=AR0, AR0->FR1, AR2->trap_out_lo, ARP=AR2
     264            ;----------------------------------------------------------------------------------
     265 005c be03          PAC                             ; ACC = (1/8192)*(trap_max_tmp-trap_min_tmp)  (Q29)
     266                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     267            ;----------------------------------------------------------------------------------
     268 005d be02                  NEG                             ; ACC = -(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q29)
     269                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     270            ;----------------------------------------------------------------------------------
     271 005e be09                  SFL                             ; ACC = -(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q30)
     272                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     273            ;----------------------------------------------------------------------------------
     274 005f be09                  SFL                             ; ACC = -(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q31)
     275                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     276            ;----------------------------------------------------------------------------------
     277 0060 62a0          ADDS    *+              ; ACC = trap_out-(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q31)
     278                                                    ; ARP=AR2, AR0->FR1, AR2->trap_out
     279            ;----------------------------------------------------------------------------------
     280 0061 6180          ADDH    *               ; ACC = trap_out-(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q31)
     281                                                    ; ARP=AR2, AR0->FR1, AR2->trap_out
     282            ;----------------------------------------------------------------------------------
     283 0062 9890          SACH    *-              ; trap_out = trap_out-(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q31)
     284                                                    ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     285            ;----------------------------------------------------------------------------------
     286 0063 9080          SACL    *               ; trap_out = trap_out-(1/8192)*(trap_max_tmp-trap_min_tmp)  (Q31)
     287                                                    ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     288            ;----------------------------------------------------------------------------------
     289 0064 7c08                  SBRK    #8              ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr
     290            ;----------------------------------------------------------------------------------
     291 0065 7980          B       RESET_DELAY  ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr 
         0066 006d' 
     292            ;----------------------------------------------------------------------------------
     293 0067       MIN_TRAP                ; ARP=AR2, AR0->FR1, AR2->trap_timer
     294            ;----------------------------------------------------------------------------------
     295 0067 7805                  ADRK    #5              ; ARP=AR2, AR0->FR1, AR2->trap_min_tmp
     296            ;----------------------------------------------------------------------------------
     297 0068 6a80          LACC    *,16    ; ACC = trap_min_tmp  (Q15)
     298                                                    ; ARP=AR2, AR0->FR1, AR2->trap_min_tmp
     299            ;----------------------------------------------------------------------------------
     300 0069 7802          ADRK    #2              ; ARP=AR2, AR0->FR1, AR2->trap_out
     301            ;----------------------------------------------------------------------------------
     302 006a 9890                  SACH    *-              ; trap_out = trap_min_tmp  (Q15)
     303                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     304            ;----------------------------------------------------------------------------------
     305 006b 9080                  SACL    *               ; trap_out = trap_min_tmp  (Q15)
     306                                                            ; ARP=AR2, AR0->FR1, AR2->trap_out_lo
     307            ;----------------------------------------------------------------------------------
     308 006c 7c08                  SBRK    #8              ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr 
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:22 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
trap_gen.asm                                                         PAGE    7

     309            ;----------------------------------------------------------------------------------
     310 006d       RESET_DELAY                     ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr
     311            ;----------------------------------------------------------------------------------
     312 006d ae80                  SPLK    #0,*    ; trap_delay_cntr = 0 (reset delay counter)  (Q0)       
         006e 0000  
     313                                    ; ARP=AR2, AR0->FR1, AR2->trap_delay_cntr                
     314            ;----------------------------------------------------------------------------------
     315 006f       TRAP_EXIT
     316            ;----------------------------------------------------------------------------------
     317 006f       _trapgen_calc_exit:
     318 006f 8b89          MAR     *,AR1   ; can be removed if this condition is met on
     319                                    ; every path to this code. (i.e., ARP=AR1 here)
     320            
     321 0070 be42          CLRC    OVM
     322 0071 be46          CLRC    SXM
     323            
     324 0072 7c03          SBRK    #(__trapgen_calc_framesize+1)
     325 0073 0090          LAR     AR0,*-
     326 0074 7680          PSHD    *
     327                    
     328 0075 ef00          RET
     329            
     330            
     331            

 No Errors,  No Warnings