📄 svgen_mf.lst
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428 ; ARP=AR2. AR0->FR3 and AR2->va
429 ;--------------------------------------------------------------------------------
430 009a 1088 LACC *,AR0 ; get va.
431 ; ARP=AR0. AR0->FR3 and AR2->va
432 ;--------------------------------------------------------------------------------
433 009b 20aa ADD *+,AR2 ; ACC=va+dy.
434 ; ARP=AR2. AR0->FR4 and AR2->va
435 ;--------------------------------------------------------------------------------
436 009c 7802 ADRK #2 ; ARP=AR2. AR0->FR4 and AR2->vc
437 ;--------------------------------------------------------------------------------
438 009d 9080 SACL * ; store vc
439 ; ARP=AR2. AR0->FR4 and AR2->vc
440 ;--------------------------------------------------------------------------------
441 009e 7980 B __SVGEN_gen_outputs
009f 00a0'
442 ; ARP=AR2. AR0->FR4 and AR2->vc
443 ;--------------------------------------------------------------------------------
444 00a0 __SVGEN_gen_outputs:
445 ; on entry from all sector sub-routines,
446 ; ARP=AR2. AR0->FR4 and AR2->vc
447 ; post processing is as follows:
448 ; V?=(V?-3fffh)*2*gain.
449 ; ? => a, b, and c.
450 ;--------------------------------------------------------------------------------
451 00a0 1080 LACC * ; get vc.
452 ; ARP=AR2. AR0->FR4 and AR2->vc
453 ;--------------------------------------------------------------------------------
454 00a1 bfa0 SUB #3fffh ; vc-3fffh
00a2 3fff
455 ; ARP=AR2. AR0->FR4 and AR2->vc
456 ;--------------------------------------------------------------------------------
457 00a3 9090 SACL *- ; store vc-3fffh
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:11 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_mf.asm PAGE 10
458 ; ARP=AR2. AR0->FR4 and AR2->vb
459 ;--------------------------------------------------------------------------------
460 00a4 1080 LACC * ; get vb.
461 ; ARP=AR2. AR0->FR4 and AR2->vb
462 ;--------------------------------------------------------------------------------
463 00a5 bfa0 SUB #3fffh ; vb-3fffh
00a6 3fff
464 ; ARP=AR2. AR0->FR4 and AR2->vb
465 ;--------------------------------------------------------------------------------
466 00a7 9090 SACL *- ; store vb-3fffh
467 ; ARP=AR2. AR0->FR4 and AR2->va
468 ;--------------------------------------------------------------------------------
469 00a8 1080 LACC * ; get va.
470 ; ARP=AR2. AR0->FR4 and AR2->va
471 ;--------------------------------------------------------------------------------
472 00a9 bfa0 SUB #3fffh ; va-3fffh
00aa 3fff
473 ; ARP=AR2. AR0->FR4 and AR2->va
474 ;--------------------------------------------------------------------------------
475 00ab 9080 SACL * ; store va-3fffh
476 ; ARP=AR2. AR0->FR4 and AR2->(va-3fffh)
477 ;--------------------------------------------------------------------------------
478 00ac 7c05 SBRK #5 ; ARP=AR2. AR0->FR4 and AR2->gain
479 ;--------------------------------------------------------------------------------
480 00ad 7380 LT * ; TREG=gain
481 ; ARP=AR2. AR0->FR4 and AR2->gain
482 ;--------------------------------------------------------------------------------
483 00ae 7805 ADRK #5 ; ARP=AR2. AR0->FR4 and AR2->(va-3fffh)
484 ;--------------------------------------------------------------------------------
485 00af 5480 MPY * ; P=gain*(va-3fffh).
486 ; ARP=AR2. AR0->FR4 and AR2->(va-3fffh)
487 ;--------------------------------------------------------------------------------
488 00b0 be03 PAC ; ACC=gain*(va-3fffh)
489 ; SPM=1 already, and removes extra sign bit.
490 ; ARP=AR2. AR0->FR4 and AR2->(va-3fffh)
491 ;--------------------------------------------------------------------------------
492 00b1 be04 APAC ; ACC=2*gain*(va-3fffh)
493 ; ARP=AR2. AR0->FR4 and AR2->(va-3fffh)
494 ;--------------------------------------------------------------------------------
495 00b2 98a0 SACH *+ ; store 2*gain*(va-3fffh)=va_final_value,
496 ; ARP=AR2. AR0->FR4 and AR2->(vb-3fffh)
497 ;--------------------------------------------------------------------------------
498 00b3 5480 MPY * ; P=gain*(vb-3fffh).
499 ; ARP=AR2. AR0->FR4 and AR2->(vb-3fffh)
500 ;--------------------------------------------------------------------------------
501 00b4 be03 PAC ; ACC=gain*(vb-3fffh)
502 ; SPM=1 already, and removes extra sign bit.
503 ; ARP=AR2. AR0->FR4 and AR2->(vb-3fffh)
504 ;--------------------------------------------------------------------------------
505 00b5 be04 APAC ; ACC=2*gain*(vb-3fffh)
506 ; ARP=AR2. AR0->FR4 and AR2->(vb-3fffh)
507 ;--------------------------------------------------------------------------------
508 00b6 98a0 SACH *+ ; store 2*gain*(vb-3fffh)=vb_final_value,
509 ; ARP=AR2. AR0->FR4 and AR2->(vc-3fffh)
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:11 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_mf.asm PAGE 11
510 ;--------------------------------------------------------------------------------
511 00b7 5480 MPY * ; P=gain*(vc-3fffh).
512 ; ARP=AR2. AR0->FR4 and AR2->(vc-3fffh)
513 ;--------------------------------------------------------------------------------
514 00b8 be03 PAC ; ACC=gain*(vc-3fffh)
515 ; SPM=1 already, and removes extra sign bit.
516 ; ARP=AR2. AR0->FR4 and AR2->(vc-3fffh)
517 ;--------------------------------------------------------------------------------
518 00b9 be04 APAC ; ACC=2*gain*(vc-3fffh)
519 ; ARP=AR2. AR0->FR4 and AR2->(vc-3fffh)
520 ;--------------------------------------------------------------------------------
521 00ba 9889 SACH *,AR1 ; store 2*gain*(vc-3fffh)=vc_final_value,
522 ; ARP=AR1. AR0->FR4 and AR2->(vc-3fffh)
523
524 ; Note: ARP=AR1 in prep for exit.
525 ;================================================================================
526 00bb __Space_Vector_Gen_exit:
527 00bb bf00 SPM 0 ; restore compiler product mode setting.
528
529 00bc 7c06 SBRK #(__SVGEN_framesize+1)
530 00bd 0090 LAR AR0,*-
531 00be 7680 PSHD *
532 00bf ef00 RET
533
534 00c0 _SVGEN_SECTOR_TABLE:
535
536 00c0 003e' .word __SVGEN_Sector1
537 00c1 004e' .word __SVGEN_Sector2
538 00c2 005d' .word __SVGEN_Sector3
539 00c3 006d' .word __SVGEN_Sector4
540 00c4 007e' .word __SVGEN_Sector5
541 00c5 008f' .word __SVGEN_Sector6
542
543 ;-------------------------------------------------------
544 ;Sine table (0 - 60 deg) used for Space Vector Generator.
545 ;No. Samples 256 Angle Range 60
546 ;-------------------------------------------------------
547 ; SINVAL ; Index Angle Sin(Angle)
548 00c6 _SINE_TABLE_60:
549
550 00c6 0000 .word 0 ; 0 0 0.00
551 00c7 0086 .word 134 ; 1 0.23 0.00
552 00c8 010c .word 268 ; 2 0.47 0.01
553 00c9 0192 .word 402 ; 3 0.70 0.01
554 00ca 0218 .word 536 ; 4 0.94 0.02
555 00cb 029e .word 670 ; 5 1.17 0.02
556 00cc 0324 .word 804 ; 6 1.41 0.02
557 00cd 03aa .word 938 ; 7 1.64 0.03
558 00ce 0430 .word 1072 ; 8 1.88 0.03
559 00cf 04b6 .word 1206 ; 9 2.11 0.04
560 00d0 053c .word 1340 ; 10 2.34 0.04
561 00d1 05c2 .word 1474 ; 11 2.58 0.04
562 00d2 0648 .word 1608 ; 12 2.81 0.05
563 00d3 06ce .word 1742 ; 13 3.05 0.05
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Tue May 6 12:41:11 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_mf.asm PAGE 12
564 00d4 0754 .word 1876 ; 14 3.28 0.06
565 00d5 07d9 .word 2009 ; 15 3.52 0.06
566 00d6 085f .word 2143 ; 16 3.75 0.07
567 00d7 08e5 .word 2277 ; 17 3.98 0.07
568 00d8 096b .word 2411 ; 18 4.22 0.07
569 00d9 09f0 .word 2544 ; 19 4.45 0.08
570 00da 0a76 .word 2678 ; 20 4.69 0.08
571 00db 0afb .word 2811 ; 21 4.92 0.09
572 00dc 0b81 .word 2945 ; 22 5.16 0.09
573 00dd 0c06 .word 3078 ; 23 5.39 0.09
574 00de 0c8c .word 3212 ; 24 5.63 0.10
575 00df 0d11 .word 3345 ; 25 5.86 0.10
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