svgen_mf.lst

TI的digital motor control lib的源代码。了解TI的编程规范

     286            ;--------------------------------------------------------------------------------
     287 005f 30a0                  SUB     *+      ; ACC=1-dy
     288                                            ; ARP=AR0. AR0->FR4 and AR2->sector_ptr
     289            ;--------------------------------------------------------------------------------
     290 0060 308a                  SUB     *,AR2   ; ACC=1-dy-dx.
     291                                            ; ARP=AR2. AR0->FR4 and AR2->sector_ptr
     292            ;--------------------------------------------------------------------------------
     293 0061 be0a                  SFR             ; ACC=(1-dy-dx)/2.
     294                                            ; ARP=AR2. AR0->FR4 and AR2->sector_ptr
     295            ;--------------------------------------------------------------------------------
     296 0062 7802                  ADRK    #2      ; ARP=AR2. AR0->FR4 and AR2->vb.
     297            ;--------------------------------------------------------------------------------
     298 0063 90a8                  SACL    *+,AR0  ; store vb
     299                                            ; ARP=AR0. AR0->FR4 and AR2->vc.
     300            ;--------------------------------------------------------------------------------
     301 0064 208a                  ADD     *,AR2   ; Acc=(bv+dx)
     302                                            ; ARP=AR2. AR0->FR4 and AR2->vc.
     303            ;--------------------------------------------------------------------------------
     304 0065 9090                  SACL    *-      ; store vc
     305                                            ; ARP=AR2. AR0->FR4 and AR2->vb.
     306            ;--------------------------------------------------------------------------------
     307 0066 bf80                  LACC    #7fffh  ; ACC=1.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_mf.asm                                                         PAGE    7

         0067 7fff  
     308                                            ; ARP=AR2. AR0->FR4 and AR2->vb.
     309            ;--------------------------------------------------------------------------------
     310 0068 3090                  SUB     *-      ; ACC=1-vb
     311                                            ; ARP=AR2. AR0->FR4 and AR2->va.
     312            ;--------------------------------------------------------------------------------
     313 0069 9080                  SACL    *       ; store va.
     314                                            ; ARP=AR2. AR0->FR4 and AR2->va.
     315            ;--------------------------------------------------------------------------------
     316 006a 7802                  ADRK    #2      ; ARP=AR2. AR0->FR4 and AR2->vc.
     317            ;--------------------------------------------------------------------------------
     318 006b 7980                  B      __SVGEN_gen_outputs
         006c 00a0' 
     319                                            ; ARP=AR2. AR0->FR4 and AR2->vc.
     320            
     321            ;--------------------------------------------------------------------------------
     322 006d       __SVGEN_Sector4:                ; on entry: ARP=AR0. AR0->FR3 and AR2->sector_ptr
     323            
     324 006d bf80                  LACC    #7fffh  ; ACC=1.
         006e 7fff  
     325                                            ; ARP=AR0. AR0->FR3 and AR2->sector_ptr
     326            ;--------------------------------------------------------------------------------
     327 006f 30a0                  SUB     *+      ; ACC=1-dy
     328                                            ; ARP=AR0. AR0->FR4 and AR2->sector_ptr
     329            ;--------------------------------------------------------------------------------
     330 0070 309a                  SUB     *-,AR2  ; ACC=1-dy-dx
     331                                            ; ARP=AR2. AR0->FR3 and AR2->sector_ptr
     332            ;--------------------------------------------------------------------------------
     333 0071 be0a                  SFR             ; ARP=AR2. AR0->FR3 and AR2->sector_ptr
     334            ;--------------------------------------------------------------------------------
     335 0072 7803                  ADRK    #3      ; ARP=AR2. AR0->FR3 and AR2->vc
     336            ;--------------------------------------------------------------------------------
     337 0073 9098                  SACL    *-,AR0  ; store vc.
     338                                            ; ARP=AR0. AR0->FR3 and AR2->vb
     339            ;--------------------------------------------------------------------------------
     340 0074 208a                  ADD     *,AR2   ; ACC=(vc+dy)
     341                                            ; ARP=AR2. AR0->FR3 and AR2->vb
     342            ;--------------------------------------------------------------------------------
     343 0075 90a0                  SACL    *+      ; store vb
     344                                            ; ARP=AR2. AR0->FR3 and AR2->vc
     345            ;--------------------------------------------------------------------------------
     346 0076 bf80                  LACC    #7fffh  ; ACC=1.
         0077 7fff  
     347                                            ; ARP=AR2. AR0->FR3 and AR2->vc
     348            ;--------------------------------------------------------------------------------
     349 0078 3080                  SUB     *       ; ACC=1-vc.
     350                                            ; ARP=AR2. AR0->FR3 and AR2->vc
     351            ;--------------------------------------------------------------------------------
     352 0079 7c02                  SBRK    #2      ;
     353                                            ; ARP=AR2. AR0->FR3 and AR2->va
     354            ;--------------------------------------------------------------------------------
     355 007a 9080                  SACL    *       ; store Va
     356                                            ; ARP=AR2. AR0->FR3 and AR2->va
     357            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_mf.asm                                                         PAGE    8

     358 007b 7802                  ADRK    #2      ; ARP=AR2. AR0->FR3 and AR2->vc
     359            ;--------------------------------------------------------------------------------
     360 007c 7980                  B      __SVGEN_gen_outputs
         007d 00a0' 
     361            ;--------------------------------------------------------------------------------
     362 007e       __SVGEN_Sector5:                ; on entry: ARP=AR0. AR0->FR3 and AR2->sector_ptr
     363            
     364            
     365 007e bf80                  LACC    #7fffh  ; ACC=1.
         007f 7fff  
     366                                            ; ARP=AR0. AR0->FR3 and AR2->sector_ptr
     367            ;--------------------------------------------------------------------------------
     368 0080 30a0                  SUB     *+      ; ACC=1-dy
     369                                            ; ARP=AR0. AR0->FR4 and AR2->sector_ptr
     370            ;--------------------------------------------------------------------------------
     371 0081 308a                  SUB     *,AR2  ; ACC=1-dy-dx
     372                                            ; ARP=AR2. AR0->FR4 and AR2->sector_ptr
     373            ;--------------------------------------------------------------------------------
     374 0082 be0a                  SFR             ; ARP=AR2. AR0->FR4 and AR2->sector_ptr
     375            ;--------------------------------------------------------------------------------
     376 0083 7803                  ADRK    #3      ; ARP=AR2. AR0->FR4 and AR2->vc
     377            ;--------------------------------------------------------------------------------
     378 0084 9088                  SACL    *,AR0   ; store vc.
     379                                            ; ARP=AR0. AR0->FR4 and AR2->vc
     380            ;--------------------------------------------------------------------------------
     381 0085 208a                  ADD     *,AR2   ; ACC=(vc+dx).
     382                                            ; ARP=AR2. AR0->FR4 and AR2->vc
     383            ;--------------------------------------------------------------------------------
     384 0086 7c02                  SBRK    #2      ; ARP=AR2. AR0->FR4 and AR2->va
     385            ;--------------------------------------------------------------------------------
     386 0087 9080                  SACL    *       ; store Va
     387            ;--------------------------------------------------------------------------------
     388 0088 7802                  ADRK    #2      ; ARP=AR2. AR0->FR4 and AR2->vc
     389            ;--------------------------------------------------------------------------------
     390 0089 bf80                  LACC    #7fffh  ; ACC=1
         008a 7fff  
     391                                            ; ARP=AR2. AR0->FR4 and AR2->vc
     392            ;--------------------------------------------------------------------------------
     393 008b 3090                  SUB     *-      ; ACC=1-vc
     394                                            ; ARP=AR2. AR0->FR4 and AR2->vb
     395            ;--------------------------------------------------------------------------------
     396 008c 90a0                  SACL    *+      ; Store vb.
     397                                            ; ARP=AR2. AR0->FR4 and AR2->vc
     398            ;--------------------------------------------------------------------------------
     399 008d 7980                  B      __SVGEN_gen_outputs
         008e 00a0' 
     400                                            ; ARP=AR2. AR0->FR4 and AR2->vc
     401            ;--------------------------------------------------------------------------------
     402 008f       __SVGEN_Sector6:                ; on entry: ARP=AR0. AR0->FR3 and AR2->sector_ptr
     403            ;--------------------------------------------------------------------------------
     404 008f bf80                  LACC    #7fffh  ; ACC=1
         0090 7fff  
     405                                            ; ARP=AR0. AR0->FR3 and AR2->sector_ptr
     406            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_mf.asm                                                         PAGE    9

     407 0091 30a0                  SUB     *+      ; ACC=1-dy
     408                                            ; ARP=AR0. AR0->FR4 and AR2->sector_ptr
     409            ;--------------------------------------------------------------------------------
     410 0092 309a                  SUB     *-,AR2  ; ACC=1-dy-dx
     411                                            ; ARP=AR2. AR0->FR3 and AR2->sector_ptr
     412            ;--------------------------------------------------------------------------------
     413 0093 be0a                  SFR             ; ACC=(1-dy-dx)/2.
     414                                            ; ARP=AR2. AR0->FR3 and AR2->sector_ptr
     415            ;--------------------------------------------------------------------------------
     416 0094 7801                  ADRK    #1      ; ARP=AR2. AR0->FR3 and AR2->va
     417            ;--------------------------------------------------------------------------------
     418 0095 9080                  SACL    *       ; store va.
     419                                            ; ARP=AR2. AR0->FR3 and AR2->va
     420            ;--------------------------------------------------------------------------------
     421 0096 bf80                  LACC    #7fffh  ; ACC=1.
         0097 7fff  
     422                                            ; ARP=AR2. AR0->FR3 and AR2->va
     423            ;--------------------------------------------------------------------------------
     424 0098 30a0                  SUB     *+      ; ACC=1-va.
     425                                            ; ARP=AR2. AR0->FR3 and AR2->vb
     426            ;--------------------------------------------------------------------------------
     427 0099 9090                  SACL    *-      ; store vb.