speed_pr.lst

TI的digital motor control lib的源代码。了解TI的编程规范

         0019 7fff  
     110                                                    ; ARP=AR0, AR0->FR0, AR2->shift
     111            ;----------------------------------------------------------------------------------
     112 001a 9080          SACL    *               ; FR0 = event_period = 7FFFh + time_stamp - time_stamp_old
     113                                                    ; ARP=AR0, AR0->FR0, AR2->shift 
     114            ;----------------------------------------------------------------------------------
     115            ; Calculate speed, i.e., speed = 1/period 
     116            ; Numeraor (i.e., 1) is treated as a Q31 value, speed in Q31 (=Q31/Q0)
     117            ; Phase 1
     118            ;----------------------------------------------------------------------------------
     119 001b       CALC_SPEED              ; ARP=AR0, AR0->FR0, AR2->shift
     120            ;----------------------------------------------------------------------------------
     121 001b bf80          LACC    #07FFFh ; ACC = 7FFFh (load numerator high)
         001c 7fff  
     122                                                    ; ARP=AR0, AR0->FR0, AR2->shift
     123            ;----------------------------------------------------------------------------------
     124 001d bb0f          RPT             #15             ; Repeat next instuction 16 times
     125                                                    ; ARP=AR0, AR0->FR0, AR2->shift 
     126            ;----------------------------------------------------------------------------------
     127 001e 0a80          SUBC    *               ; Division operation (FR0 = event_period)
     128                                                    ; ARP=AR0, AR0->FR0, AR2->shift
     129            ;----------------------------------------------------------------------------------
     130 001f 7801                  ADRK    #1              ; ARP=AR0, AR0->FR1, AR2->shift
     131            ;----------------------------------------------------------------------------------
     132 0020 9080          SACL    *               ; FR1 = speed_hi = ACC low
     133                                                    ; ARP=AR0, AR0->FR1, AR2->shift
     134            ;----------------------------------------------------------------------------------
     135 0021 6c90          XOR             *-              ; XOR with speed_hi
     136                                                    ; ARP=AR0, AR0->FR0, AR2->shift
     137            ;----------------------------------------------------------------------------------
     138 0022 bfc0          OR              #0FFFFh ; load numerator low 
         0023 ffff  
     139                                                    ; ARP=AR0, AR0->FR0, AR2->shift
     140            ;----------------------------------------------------------------------------------
     141            ; Phase 2
     142            ;----------------------------------------------------------------------------------
     143 0024 bb0f                  RPT             #15             ; Repeat next instuction 16 times
     144                                                    ; ARP=AR0, AR0->FR0, AR2->shift 
     145            ;----------------------------------------------------------------------------------
     146 0025 0a80          SUBC    *               ; Division operation (FR0 = event_period)
     147                                                    ; ARP=AR0, AR0->FR0, AR2->shift 
     148            ;----------------------------------------------------------------------------------
     149 0026 7802                  ADRK    #2              ; ARP=AR0, AR0->FR2, AR2->shift
     150            ;----------------------------------------------------------------------------------
     151 0027 9080          SACL    *               ; FR2 = speed_lo = ACC low
     152                                                    ; ARP=AR0, AR0->FR2, AR2->shift
     153            ;----------------------------------------------------------------------------------
     154 0028 1090          LACC    *-              ; ACC = speed_lo
     155                                                    ; ARP=AR0, AR0->FR1, AR2->shift
     156            ;----------------------------------------------------------------------------------
     157 0029 618a                  ADDH    *,AR2   ; ACC = speed_hi + speed_lo 
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
speed_pr.asm                                                         PAGE    4

     158                                    ; ARP=AR0, AR0->FR1, AR2->shift, ARP=AR2
     159            ;----------------------------------------------------------------------------------
     160 002a 0b88                  RPT             *,AR0   ; Repeat next instuction "shift" times 
     161                                                            ; ARP=AR2, AR0->FR1, AR2->shift, ARP=AR0
     162            ;----------------------------------------------------------------------------------
     163 002b be09                  SFL                             ; Left shift in ACC
     164                                                            ; ARP=AR0, AR0->FR1, AR2->shift
     165            ;----------------------------------------------------------------------------------
     166 002c 7802          ADRK    #2              ; ARP=AR0, AR0->FR3, AR2->shift
     167            ;----------------------------------------------------------------------------------
     168 002d 98aa          SACH    *+,AR2  ; FR3 = speed_prd_max
     169                                                    ; ARP=AR0, AR0->FR4, AR2->shift, ARP=AR2
     170            ;----------------------------------------------------------------------------------
     171 002e bf80          LACC    #SHIFT_TOTAL ; ACC = SHIFT_TOTAL
         002f 000e  
     172                                                    ; ARP=AR2, AR0->FR4, AR2->shift
     173            ;----------------------------------------------------------------------------------
     174 0030 30a8                  SUB             *+,AR0  ; ACC = SHIFT_TOTAL - shift
     175                                                    ; ARP=AR2, AR0->FR4, AR2->speed_scaler, ARP=AR0 
     176            ;----------------------------------------------------------------------------------
     177 0031 9090                  SACL    *-              ; FR4 = shift2 = SHIFT_TOTAL - shift
     178                                                            ; ARP=AR0, AR0->FR3, AR2->speed_scaler
     179            ;----------------------------------------------------------------------------------
     180 0032 73aa          LT              *+,AR2  ; TREG = speed_prd_max
     181                                                    ; ARP=AR0, AR0->FR4, AR2->speed_scaler, ARP=AR2 
     182            ;----------------------------------------------------------------------------------
     183 0033 54a8                  MPY             *+,AR0  ; PREG = speed_prd_max*speed_scaler
     184                                                    ; ARP=AR2, AR0->FR4, AR2->speed_prd, ARP=AR0
     185            ;----------------------------------------------------------------------------------
     186 0034 be03          PAC                             ; ACC = speed_prd_max*speed_scaler
     187                                                    ; ARP=AR0, AR0->FR4, AR2->speed_prd     
     188            ;----------------------------------------------------------------------------------
     189 0035 0b8a          RPT             *,AR2   ; Repeat next instuction "shift2" times 
     190                                                            ; ARP=AR0, AR0->FR4, AR2->speed_prd, ARP=AR2
     191            ;----------------------------------------------------------------------------------
     192 0036 be09          SFL                             ; Left shift in ACC
     193                                                    ; ARP=AR2, AR0->FR4, AR2->speed_prd 
     194            ;----------------------------------------------------------------------------------
     195 0037 9880          SACH    *               ; speed_prd = ACC high
     196                                                    ; ARP=AR2, AR0->FR4, AR2->speed_prd 
     197            ;----------------------------------------------------------------------------------
     198 0038 73a0          LT              *+              ; TREG = speed_prd  (Q15)
     199                                                    ; ARP=AR2, AR0->FR4, AR2->rpm_max  
     200            ;----------------------------------------------------------------------------------
     201 0039 54a0          MPY             *+              ; PREG = speed_prd*rpm_max   (Q15)
     202                                                    ; ARP=AR2, AR0->FR4, AR2->speed_rpm     
     203            ;----------------------------------------------------------------------------------
     204 003a be03          PAC                             ; ACC = speed_prd*rpm_max   (Q15)
     205                                                    ; ARP=AR2, AR0->FR4, AR2->speed_rpm     
     206            ;----------------------------------------------------------------------------------
     207 003b 9989          SACH    *,1,AR1 ; speed_rpm = speed_prd*rpm_max   (Q0)
     208                                                    ; ARP=AR2, AR0->FR4, AR2->speed_rpm, ARP=AR1
     209            ;----------------------------------------------------------------------------------
     210 003c       __speed_prd_exit:
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Tue May  6 12:41:11 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
speed_pr.asm                                                         PAGE    5

     211                    ;; MAR     *,AR1   ; can be removed if this condition is met on
     212                                   ; every path to this code. (i.e., ARP=AR1 here)
     213                                   
     214 003c 7c06          SBRK    #(__speed_prd_framesize+1)
     215 003d 0090          LAR     AR0,*-
     216 003e 7680          PSHD    *
     217 003f ef00          RET
     218            

 No Errors,  No Warnings