📄 apb_i2c_module.c
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/********************************************/
/* I2CFunc.c: implementation of the I2C API.*/
/* Author : DQ */
/* Time : 2005-12-15 */
/********************************************/
#include "apb_i2c_module.h"
#include "apb_i2c_tvin.h"
#include <linux/major.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/blkdev.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#define PHY_SYS_BASE 0x20020000
#define PHY_I2C_BASE 0x20036000
unsigned int *g_i2c_base;
/*
** Brief: Initialize of the i2c master
**/
static void i2c_mst_initialize(const INITINFOR Init_data, const SCLVALUE scl_InitData , const unsigned short target_addr)
{
//Disable the I2C MASTER
I2C_DISABLE;
//Set the address if targeted as a slave
I2C_SAR(Init_data.addr);
//Set the control register for the transfer
I2C_CON(Init_data.control);
//-: Set the High period for the SCL
//(we have 10 MHz ic_clk) if we want 100kbps , SS_HCNT = 0x0028
//Set the Low period for the SCL
//(we have 10 MHz ic_clk) if we want 100kbps , SS_LCNG =0x002f
switch(scl_InitData.mode){
case I2C_SS:
I2C_SS_HCNT((scl_InitData.hcnt));
I2C_SS_LCNT(scl_InitData.lcnt);
break;
case I2C_FS:
I2C_FS_HCNT(scl_InitData.hcnt);
I2C_FS_LCNT(scl_InitData.lcnt);
break;
case I2C_HS:
I2C_HS_HCNT(scl_InitData.hcnt);
I2C_HS_LCNT(scl_InitData.lcnt);
break;
default:
I2C_ERROR("There is no the I2C mode.");
break;
}
//Set the address for the target slave
I2C_TAR(target_addr);
//Enable interrupts
I2C_INTR_MASK(Init_data.mask);
//Set Rx FIFO Threshold
I2C_RX_TL(Init_data.rx);
//Set Tx FIFO Threshold
I2C_TX_TL(Init_data.tx);
//Enable the I2C MASTER
I2C_ENABLE;
}
/* The following API are used to access the State Register*/
/*
// Receive FIFO Completely Full
bool isRFF(void)
{
bool ret;
unsigned int RegContent;
// Get the state of the State Register.
RegContent = (I2C_STATUS)&(RFF);
if(RegContent > 0)
ret = true;
ret = false ;
return ret;
}
*/
// Receive FIFO Not Empty
bool isRFNE(void)
{
unsigned int RegContent;
RegContent=((I2C_STATUS) & (RFNE));
if (RegContent == RFNE ) return true;
else return false;
}
/*
bool isRFNE(void)
{
bool ret;
unsigned int RegContent;
// Get the state of the State Register.
RegContent = (I2C_STATUS)&(RFNE);
if(RegContent > 0)
ret = true;
ret = false ;
return ret;
}
*/
// Transmit FIFO Completely Empty
bool isTFE(void)
{
bool ret;
unsigned int RegContent;
// Get the state of the State Register.
RegContent = (I2C_STATUS)&(TFE);
if(RegContent > 0) return false;
return true;
// return ret;
}
// Transmit FIFO Not Full
/*
bool isTFNF(void)
{
bool ret;
unsigned int RegContent;
// Get the state of the State Register.
RegContent = (I2C_STATUS)&(TFNF);
if(RegContent > 0)
ret = true;
ret = false ;
return ret;
}
// I2C activity state
bool issActivity(void)
{
bool ret;
unsigned int RegContent;
// Get the state of the State Register.
RegContent = (I2C_STATUS)&(sACTIVITY);
if(RegContent > 0)
ret = true;
ret = false ;
return ret;
}
*/
//end the state Register API
/* brief : Initialize the I2C module */
void init_i2c(void){
//Define the Initialize parameters
INITINFOR g_initData;
SCLVALUE g_sclData;
unsigned short g_target;
//Init global vairable (default)
g_initData.addr = 0x0045;
g_initData.control = 0x0003;
g_initData.mask = 0x0000;
g_initData.rx = 0x0000;
g_initData.tx = 0x0000;
g_sclData.mode = I2C_SS;
// g_sclData.hcnt = 0x0028;
// g_sclData.lcnt = 0x002f;
g_sclData.hcnt = 0x0088;
g_sclData.lcnt = 0x008f;
g_target = 0x0056;
g_i2c_base = (unsigned long *)(ioremap(PHY_I2C_BASE, 4096 ));
i2c_mst_initialize(g_initData, g_sclData, g_target);
}
/* brief : Delete the I2C module from the system */
void dele_i2c(void){
iounmap(g_i2c_base);
}
/* brief: This API is used to transmit data
** para : threhold -- the threhole of the FIFO
** para : buffer -- the pointer of data
** para : target -- the address of the target
** ret : retvalue is 1 means , threhold value is not illegal;
*/
int transmitData(const int threhold, const unsigned char buffer[], const unsigned short target)
{
int retValue = 0 ,i;
if(threhold < 0 || threhold >255){
retValue = 1;
return retValue;
}
I2C_DISABLE;
I2C_TX_TL((threhold-1));
I2C_TAR(target);
I2C_ENABLE;
while(isTFE()) mdelay(1);
i=0;
while(i < threhold)
{
I2C_WRITE (buffer[i++]);
}
while(isTFE()) mdelay(1);
return retValue;
}
int ReadI2cData(unsigned char addr, unsigned short * data , const unsigned short target)
{
int i;
int retvalue;
unsigned short tmp1,tmp2;
I2C_DISABLE;
I2C_TX_TL((4));
I2C_RX_TL((4));
I2C_TAR(target&0x02ff);
I2C_ENABLE;
while(isTFE()) mdelay(1);
SET_REG(IIC_DATA_CMD, (addr)&0x00ff);
while(isTFE()) mdelay(1);
if ((I2C_STATUS)&(TFNF)) SET_REG(IIC_DATA_CMD, 0x100);
if ((I2C_STATUS)&(TFNF)) SET_REG(IIC_DATA_CMD, 0x100);
while(!isRFNE()) mdelay(1);
tmp1 = I2C_READ;
tmp2 = I2C_READ;
data = (tmp1 << 8)| (tmp2 & 0x00ff) ;
return retvalue;
}
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