dsp16xx.md

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      return \"psw=%3\";
    }
}")


;;
;; Arithmetic Left shift

;; Start off with special case arithmetic left shift by 1,4,8 or 16.


(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=A")
        (ashift:HI (match_operand:HI 1 "register_operand" "A")
                   (const_int 1)))]
  ""
  "%0=%1<<1"
  [(set_attr "type" "special")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=A")
        (ashift:HI (match_operand:HI 1 "register_operand" "A")
                   (const_int 4)))]
  ""
  "%0=%1<<4"
  [(set_attr "type" "special")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=A")
        (ashift:HI (match_operand:HI 1 "register_operand" "A")
                   (const_int 8)))]
  ""
  "%0=%1<<8"
  [(set_attr "type" "special")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=A")
	(ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "A"))
		   (const_int 16)))]
  ""
  "%0=%1<<16"
  [(set_attr "type" "special")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=A")
        (ashift:HI (match_operand:HI 1 "general_operand" "A")
                   (const_int 16)))]
  ""
  "%0=%1<<16"
  [(set_attr "type" "special")])



;; Normal Arithmetic Shift Left


(define_expand "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "")
        (ashift:HI (match_operand:HI 1 "register_operand" "")
                   (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (!TARGET_BMU)
  {
      /* If we are shifting by a constant we can do it in 1 or more
	 1600 core shift instructions. The core instructions can
	 shift by 1, 4, 8, or 16. */
      
      if (GET_CODE(operands[2]) == CONST_INT)
	;
      else
      {
	rtx label1 = gen_label_rtx ();
	rtx label2 = gen_label_rtx ();
#if 0
	if (!dsp16xx_ashlhi3_libcall)
	  dsp16xx_ashlhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, ASHLHI3_LIBCALL);

	  emit_library_call (dsp16xx_ashlhi3_libcall, 1, HImode, 2,
			     operands[1], HImode,
			     operands[2], QImode);
	  emit_move_insn (operands[0], hard_libcall_value(HImode));
	  DONE;
#else
	do_pending_stack_adjust ();
	emit_insn (gen_tstqi (operands[2]));
	emit_jump_insn (gen_bne (label1));
	emit_move_insn (operands[0], operands[1]);
	emit_jump_insn (gen_jump (label2));
	emit_barrier ();
	emit_label (label1);

	if (GET_CODE(operands[2]) != MEM)
	  {
	    rtx stack_slot;
	    
	    stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0);
	    stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0));
	    emit_move_insn (stack_slot, operands[2]);
	    operands[2] = stack_slot;
	  }
	emit_insn (gen_match_ashlhi3_nobmu (operands[0], operands[1], operands[2]));
	emit_label (label2);
	DONE;
#endif
      }
  }
}")

(define_insn "match_ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
        (ashift:HI (match_operand:HI 1 "register_operand" "A,A,A")
                   (match_operand:QI 2 "nonmemory_operand" "B,I,!h")))]
  "TARGET_BMU"
  "@
   %0=%1<<%2\;move %u0=%u0
   %0=%1<<%H2\;move %u0=%u0
   %0=%1<<%2\;move %u0=%u0"
  [(set_attr "type" "shift,shift_i,shift")])

(define_insn "match_ashlhi3_nobmu"
  [(set (match_operand:HI 0 "register_operand" "=A,A")
        (ashift:HI (match_operand:HI 1 "register_operand" "A,0")
		   (match_operand:QI 2 "general_operand" "n,m")))]
  "!TARGET_BMU"
  "*
{
  if (which_alternative == 0)
    {
      emit_1600_core_shift (ASHIFT, operands, INTVAL(operands[2]));
      return \"\";
    }
  else
    {
      output_asm_insn (\"cloop=%2\", operands);
      output_asm_insn (\"do 0 \{\", operands);
      output_asm_insn (\"%0=%0<<1\", operands);
      return \"\}\";
    }
}")



;;
;; Jump Instructions
;;

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (match_dup 1)
	                  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (match_dup 1)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (match_dup 1)
	                  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (match_dup 1)
	                  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (match_dup 1)
	                  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "ble"
  [(set (pc)
	(if_then_else (le (match_dup 1)
	                  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (match_dup 1)
	                   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (match_dup 1)
	                   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (match_dup 1)
	                   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_expand "bleu"
  [(set (pc)
	(if_then_else (leu (match_dup 1)
	                   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ 
   if (dsp16xx_compare_gen == gen_compare_reg)
     operands[1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
   else
     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
}")


(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator" 
                                      [(cc0) (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  "!TARGET_NEAR_JUMP"
  "pt=%l0\;if %C1 goto pt"
  [(set_attr "type" "cond_jump")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator" 
                                      [(cc0) (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  "TARGET_NEAR_JUMP"
  "if %C1 goto %l0"
  [(set_attr "type" "cond_jump")])

;;
;; Negated conditional jump instructions.
;; These are necessary because jump optimization can turn
;; direct-conditional branches into reverse-conditional
;; branches.

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator" 
                                      [(cc0) (const_int 0)])
	              (pc)
		      (label_ref (match_operand 0 "" ""))))]
  "!TARGET_NEAR_JUMP"
  "pt=%l0\;if %I1 goto pt"
  [(set_attr "type" "cond_jump")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator" 
                                      [(cc0) (const_int 0)])
	              (pc)
		      (label_ref (match_operand 0 "" ""))))]
  "TARGET_NEAR_JUMP"
  "if %I1 goto %l0"
  [(set_attr "type" "cond_jump")])


;;
;; JUMPS
;;

(define_insn "jump"
  [(set (pc)
        (label_ref (match_operand 0 "" "")))]
  ""
  "*
   {
	if (TARGET_NEAR_JUMP)
	    return \"goto %l0\";
        else
	    return \"pt=%l0\;goto pt\";
   }"
   [(set_attr "type" "jump")])


(define_insn "indirect_jump"
  [(set (pc) (match_operand:QI 0 "register_operand" "A"))]
  ""
  "pt=%0\;goto pt"
   [(set_attr "type" "jump")])

(define_insn "tablejump"
  [(set (pc) (match_operand:QI 0 "register_operand" "A"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "pt=%0\;goto pt"
   [(set_attr "type" "jump")])

;;
;; FUNCTION CALLS
;;

;; Call subroutine with no return value.


(define_expand "call"
  [(parallel [(call (match_operand:QI 0 "" "")
	            (match_operand 1 "" ""))
	     (clobber (reg:QI 24))])]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! call_address_operand (XEXP (operands[0], 0), QImode))
    operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
			   force_reg (Pmode, XEXP (operands[0], 0)));
}")

(define_insn ""
  [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" "hR"))
	                    (match_operand 1 "" ""))
	      (clobber (reg:QI 24))])]
  ""
  "*
{
    if (GET_CODE (operands[0]) == REG || 
	(GET_CODE(operands[0]) == SYMBOL_REF && !TARGET_NEAR_CALL))
	return \"pt=%0\;call pt\";
    else
        return \"call %0\";
}"
[(set_attr "type" "call")])

;; Call subroutine with return value.

(define_expand "call_value"
  [(parallel [(set (match_operand 0 "register_operand" "=f")
		  (call (match_operand:QI 1 "call_address_operand" "hR")
	                (match_operand:QI 2 "" "")))
	      (clobber (reg:QI 24))])]
  ""
  "
{
  if (GET_CODE (operands[1]) == MEM
      && ! call_address_operand (XEXP (operands[1], 0), QImode))
    operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
			   force_reg (Pmode, XEXP (operands[1], 0)));
}")

(define_insn ""
  [(parallel [(set (match_operand 0 "register_operand" "=f")
		  (call (mem:QI (match_operand:QI 1 "call_address_operand" "hR"))
	                        (match_operand:QI 2 "" "")))
	      (clobber (reg:QI 24))])]
  ""
  "*
{
    if (GET_CODE (operands[1]) == REG ||
	(GET_CODE(operands[1]) == SYMBOL_REF && !TARGET_NEAR_CALL))
	return \"pt=%1\;call pt\";
    else
        return \"call %1\";
}"
[(set_attr "type" "call")])


(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
		    (const_int 0))
	      (match_operand 1 "" "")
	      (match_operand 2 "" "")])]
  ""
  "
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());

  DONE;
}")

;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory.  This blocks insns from being moved across this point.

(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] 0)]
  ""
  "")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop"
  [(set_attr "type"     "nop")])

;;
;; PEEPHOLE PATTERNS
;;


(define_peephole
  [(set (match_operand:QI 0 "register_operand" "=A")
        (reg:QI 16))
   (call (mem:QI (match_dup 0))
	 (match_operand 1 "" "i"))]
   ""
   "call pt")


(define_peephole
  [(set (match_operand:QI 0 "register_operand" "=A")
        (reg:QI 16))
   (set (match_operand 1 "" "")
        (call (mem:QI (match_dup 0))
	      (match_operand 2 "" "i")))]
   ""
   "call pt")

(define_peephole
  [(set (match_operand:HI 0 "register_operand" "=A")
	(ashift:HI (match_operand:HI 1 "register_operand" "A")
		   (const_int 16)))
   (set (match_operand:HI 2 "register_operand" "")
	(match_dup 0))
   (set (match_dup 0)
	(ashiftrt:HI (match_dup 0) (const_int 16)))
   (set (match_dup 2)
	(match_dup 0))]
  ""
  "%0=%1<<16\;%0=%0>>16\;%u2=%u0\;%w2=%w0")

(define_peephole
  [(set (match_operand:HI 0 "register_operand" "=A")
	(ashift:HI (match_operand:HI 1 "register_operand" "A")
		   (const_int 16)))
   (set (match_operand:HI 2 "register_operand" "")
	(match_dup 0))
   (set (match_dup 0)
	(lshiftrt:HI (match_dup 0) (const_int 16)))
   (set (match_dup 2)
	(match_dup 0))]
  ""
  "%0=%1<<16\;%0=%0>>16\;%0=%b0&0x0000\;%u2=%u0\;%w2=%w0")