dsp16xx.md

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;;- Machine description for the AT&T DSP1600 for GNU C compiler
;;  Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
;;  Contributed by Michael Collison ([e-mail]).

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;; Attribute specifications

; Type of each instruction.  Default is arithmetic.
; I'd like to write the list as this, but genattrtab won't accept it.
;
; "jump,cond_jump,call,			; flow-control instructions
;  load_i,load, store, move		; Y space address arithmetic instructions
;  malu,special,f3_alu,f3_alu_i		; data arithmetic unit instructions
;  shift_i,shift, bfield_i, bfield	; bit manipulation unit instructions
;  arith,				; integer unit instructions
;  nop

; Classification of each insn.  Some insns of TYPE_BRANCH are multi-word.
(define_attr "type"
  "jump,cond_jump,call,load_i,load,move,store,malu,malu_mul,special,f3_alu,f3_alu_i,shift_i,shift,bfield_i,bfield,nop,ld_short_i"
  (const_string "malu"))

; Length in # of instructions of each insn.  The values are not exact, but
; are safe.
(define_attr "length" ""
  (cond [(eq_attr "type" "cond_jump,f3_alu_i,shift_i,bfield_i,load_i")
	 (const_int 2)]
	(const_int 1)))


;;  ....................
;;
;;  Test against 0 instructions
;;
;;  ....................

(define_expand "tsthi"
  [(set (cc0)
        (match_operand:HI 0 "register_operand" ""))]
  ""
  "
{
  dsp16xx_compare_gen = gen_tst_reg;
  dsp16xx_compare_op0 = operands[0];
  dsp16xx_compare_op1 = const0_rtx;
  DONE;
}")

(define_insn "tsthi_1"
  [(set (cc0)
	(match_operand:HI 0 "register_operand" "A"))]
  ""
  "%0=%0"
  [(set_attr "type" "malu")])

(define_expand "tstqi"
  [(set (cc0)
        (match_operand:QI 0 "register_operand" ""))]
  ""
  "
{
  dsp16xx_compare_gen = gen_tst_reg;
  dsp16xx_compare_op0 = operands[0];
  dsp16xx_compare_op1 = const0_rtx;
  DONE;
}")

(define_insn "tstqi_1"
  [(set (cc0)
	(match_operand:QI 0 "register_operand" "j,q"))
   (clobber (match_scratch:QI 1 "=k,u"))]
  ""
  "@
   %1=0\;%b0-0
   %1=0\;%b0-0"
  [(set_attr "type" "malu,malu")])


;;
;;  ....................
;;
;;  Bit test instructions
;;
;;  ....................

(define_insn ""
  [(set (cc0)
	(and:HI (match_operand:HI 0 "register_operand" "A,!A,A")
		(match_operand:HI 1 "nonmemory_operand" "Z,A,I")))]
  "" 
  "*
{
	switch (which_alternative)
	{
	   case 0:
	   case 1:
   	      return \"%0&%1\";

	   case 2:
   	      return \"%0&%H1\";
         }
}"
  [(set_attr "type" "f3_alu,malu,f3_alu_i")])


;;(define_insn ""
;;  [(set (cc0)
;;	(and:QI (match_operand:QI 0 "register_operand" "h")
;;		(match_operand:QI 1 "const_int_operand" "I")))]
;;  "" 
;;  "%b0&%H1"
;;  [(set_attr "type" "f3_alu_i")])

;;
;;
;; Compare Instructions
;;

(define_expand "cmphi"
  [(parallel [(set (cc0)
		   (compare (match_operand:HI 0 "general_operand" "")
			    (match_operand:HI 1 "general_operand" "")))
	      (clobber (match_scratch:QI 2 ""))
	      (clobber (match_scratch:QI 3 ""))
	      (clobber (match_scratch:QI 4 ""))
	      (clobber (match_scratch:QI 5 ""))])]
  ""
  "
{
  if (GET_CODE (operands[1]) == CONST_INT)
    operands[1] = force_reg (HImode, operands[1]);

  dsp16xx_compare_gen = gen_compare_reg;
  dsp16xx_compare_op0 = operands[0];
  dsp16xx_compare_op1 = operands[1];
  DONE;
}")

(define_insn ""
  [(set (cc0) 
	(compare (match_operand:HI 0 "general_operand" "Z*r*m*i")
		 (match_operand:HI 1 "general_operand" "Z*r*m*i")))
   (clobber (match_scratch:QI 2 "=&A"))
   (clobber (match_scratch:QI 3 "=&A"))
   (clobber (match_scratch:QI 4 "=&A"))
   (clobber (match_scratch:QI 5 "=&A"))]
  "next_cc_user_unsigned (insn)"
  "*
{
  if (GET_CODE(operands[0]) == REG)
    {
      if (REGNO (operands[0]) == REG_Y ||
	  REGNO (operands[0]) == REG_PROD)
	{
	  output_asm_insn (\"a0=%0\", operands);
	}
      else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[0])))
	{
	  output_asm_insn (\"a0=%u0\;a0l=%w0\", operands);
	}
      else
	dsp16xx_invalid_register_for_compare ();
    }
  else if (GET_CODE(operands[0]) == CONST_INT)
    {
      output_asm_insn (\"a0=%U0\;a0l=%H0\", operands);
    }
  else if (GET_CODE (operands[0]) == MEM)
    {
      rtx xoperands[2];

      xoperands[0] = gen_rtx_REG (HImode, REG_A0);
      xoperands[1] = operands[0];
      double_reg_from_memory (xoperands);
    }

  if (GET_CODE(operands[1]) == REG)
    {
      if (REGNO (operands[1]) == REG_Y ||
	  REGNO (operands[1]) == REG_PROD)
	{
	  output_asm_insn (\"a1=%1\", operands);
	}
      else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[1])))
	{
	  output_asm_insn (\"a1=%u1\;a1l=%w1\", operands);
	}
      else
	dsp16xx_invalid_register_for_compare ();
    }
  else if (GET_CODE (operands[1]) == MEM)
    {
      rtx xoperands[2];

      xoperands[0] = gen_rtx_REG (HImode, REG_A1);
      xoperands[1] = operands[1];
      double_reg_from_memory (xoperands);
    }
  else if (GET_CODE(operands[1]) == CONST_INT)
    {
      output_asm_insn (\"a1=%U1\;a1l=%H1\", operands);
    }
  
  return \"psw = 0\;a0 - a1\";
}")

(define_insn ""
  [(set (cc0) (compare (match_operand:HI 0 "register_operand" "A,!A")
		       (match_operand:HI 1 "register_operand" "Z,*A")))]
  ""
  "@
   %0-%1
   %0-%1"
  [(set_attr "type" "malu,f3_alu")])

(define_expand "cmpqi"
  [(parallel [(set (cc0)
		   (compare (match_operand:QI 0 "register_operand" "")
			    (match_operand:QI 1 "nonmemory_operand" "")))
	      (clobber (match_operand:QI 2 "register_operand" ""))
	      (clobber (match_operand:QI 3 "register_operand" ""))])]
  ""
  "
 {
  if (operands[0])	/* Avoid unused code warning */
    {
      dsp16xx_compare_gen = gen_compare_reg;
      dsp16xx_compare_op0 = operands[0];
      dsp16xx_compare_op1 = operands[1];
      DONE;
    }
 }")

(define_insn ""
  [(set (cc0) (compare (match_operand:QI 0 "register_operand"  "k,k,!k,k,u,u,!u,u")
                       (match_operand:QI 1 "nonmemory_operand" "w,z,u,i,w,z,k,i")))
	(clobber (match_scratch:QI 2 "=j,j,j,j,q,q,q,q"))
	(clobber (match_scratch:QI 3 "=v,y,q,X,v,y,j,X"))]
  "next_cc_user_unsigned (insn)"
  "@
   %2=0\;%3=0\;%2-%3
   %2=0\;%3=0\;%2-%3
   %2=0\;%3=0\;%2-%3
   %2=0\;%0-%H1
   %2=0\;%3=0\;%2-%3
   %2=0\;%3=0\;%2-%3
   %2=0\;%3=0\;%2-%3
   %2=0\;%0-%H1")


(define_insn ""
  [(set (cc0) (compare (match_operand:QI 0 "register_operand"  "j,j,!j,j,q,q,!q,q")
                       (match_operand:QI 1 "nonmemory_operand" "v,y,q,i,v,y,j,i")))
	(clobber (match_scratch:QI 2 "=k,k,k,k,u,u,u,u"))
	(clobber (match_scratch:QI 3 "=w,z,u,X,w,z,k,X"))]
  ""
  "@
   %2=0\;%3=0\;%0-%1
   %2=0\;%3=0\;%0-%1
   %2=0\;%3=0\;%0-%1
   %2=0\;%b0-%H1
   %2=0\;%3=0\;%0-%1
   %2=0\;%3=0\;%0-%1
   %2=0\;%3=0\;%0-%1
   %2=0\;%b0-%H1")


(define_expand "cmphf"
  [(set (cc0)
	(compare (match_operand:HF 0 "register_operand" "")
		 (match_operand:HF 1 "nonmemory_operand" "")))]
  ""
  "
{
  if (!dsp16xx_cmphf3_libcall)
    dsp16xx_cmphf3_libcall = gen_rtx_SYMBOL_REF (Pmode, CMPHF3_LIBCALL);

   dsp16xx_compare_gen = gen_compare_reg;
   dsp16xx_compare_op0 = operands[0];
   dsp16xx_compare_op1 = operands[1];
   emit_library_call (dsp16xx_cmphf3_libcall, 1, HImode, 2,
		      operands[0], HFmode,
		      operands[1], HFmode);
   emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode))));
   DONE;
}")


;;  ....................
;;
;;  Add instructions
;;
;;  ....................


(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
	(plus:HI (match_operand:HI 1 "register_operand" "%A,A,A")
		 (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))]
  ""
  "@
   %0=%1+%2
   %0=%1+%2
   %0=%w1+%H2\;%0=%b0+%U2"
  [(set_attr "type" "malu,malu,f3_alu_i")])

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u")
	(plus:QI (plus:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk")
			  (match_operand:QI 2 "register_operand" "wz,wz,uk,uk"))
		 (match_operand:QI 3 "immediate_operand" "i,i,i,i")))
   (clobber (match_scratch:QI 4 "=j,q,j,q"))]
  ""
  "@
   %m0=%m1+%m2\;%m0=%0+%H3
   %m0=%m1+%m2\;%m0=%0+%H3
   %m0=%m1+%m2\;%m0=%0+%H3
   %m0=%m1+%m2\;%m0=%0+%H3")

(define_expand "addqi3"
  [(parallel [(set (match_operand:QI 0 "register_operand" "")
		   (plus:QI (match_operand:QI 1 "register_operand" "")
			    (match_operand:QI 2 "nonmemory_operand" "")))
	      (clobber (match_scratch:QI 3 ""))])]
  ""
  "
{
  if (reload_in_progress)
    {
      if (REG_P (operands[1]) && 
	  (REGNO(operands[1]) == STACK_POINTER_REGNUM ||
	   REGNO(operands[1]) == FRAME_POINTER_REGNUM) &&
	  GET_CODE (operands[2]) == CONST_INT)
	{
	  if (REG_P (operands[0]) && IS_ACCUM_REG(REGNO(operands[0])))
	    emit_move_insn (operands[0], operands[1]);

	  operands[1] = operands[0];
	}
    }
}")

	
(define_insn "match_addqi3"
  [(set (match_operand:QI 0 "register_operand" "=!a,!a,k,u,!k,!u,h,!a")
	(plus:QI (match_operand:QI 1 "register_operand" "0,0,uk,uk,uk,uk,h,0")
		 (match_operand:QI 2 "nonmemory_operand" "W,N,wzi,wzi,uk,uk,i,n")))
	(clobber (match_scratch:QI 3 "=X,X,j,q,j,q,X,W"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"*%0++%2\";

    case 1:
      switch (INTVAL (operands[2]))
	{
	case -1:
	  return \"*%0--\";

	case 1:
	  return \"*%0++\";

	case -2:
	  return \"*%0--\;*%0--\";

	case 2:
	  return \"*%0++\;*%0++\";
	}

    case 2:
    case 3:
      if (!CONSTANT_P(operands[2]))
        return \"%m0=%m1+%m2\";
      else
        return \"%m0=%1+%H2\";

    case 4:
    case 5:
      return \"%m0=%m1+%m2\";

    case 6:
      return \"%0=%b1+%H2\";

    case 7:
      return \"%3=%2\;*%0++%3\";
    }
}")

(define_expand "addhf3"
  [(set (match_operand:HF 0 "register_operand" "")
	(plus:HF (match_operand:HF 1 "register_operand" "")
		 (match_operand:HF 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (!dsp16xx_addhf3_libcall)
    dsp16xx_addhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, ADDHF3_LIBCALL);

   emit_library_call (dsp16xx_addhf3_libcall, 1, HFmode, 2,
		      operands[1], HFmode,
		      operands[2], HFmode);
   emit_move_insn (operands[0], hard_libcall_value(HFmode));
   DONE;
}")
		      

;;
;;  ....................
;;
;;  Subtract instructions
;;
;;  ....................

(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
	(minus:HI (match_operand:HI 1 "register_operand" "A,A,A")
		  (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))]
  ""
  "@
   %0=%1-%2
   %0=%1-%2
   %0=%w1-%H2\;%0=%b0-%U2"
  [(set_attr "type" "malu,malu,f3_alu_i")])

(define_insn "subqi3"
  [(set (match_operand:QI 0 "register_operand" "=?*a,k,u,!k,!u")
	(minus:QI (match_operand:QI 1 "register_operand" "0,uk,uk,uk,uk")
		 (match_operand:QI 2 "nonmemory_operand" "n,wzi,wzi,uk,uk")))
	(clobber (match_scratch:QI 3 "=W,j,q,j,q"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      switch (INTVAL (operands[2]))
	{
	case 0:
	  return \"\";
	  
	case 1:
	  return \"*%0--\";
	  
	case -1:
	  return \"*%0++\";
	  
	default:
	  operands[2] = GEN_INT (-INTVAL (operands[2]));
	  
	  if (SHORT_IMMEDIATE(operands[2]))
	    return \"set %3=%H2\;*%0++%3\";
	  else
	    return \"%3=%H2\;*%0++%3\";
	}
      
    case 1:
    case 2:
      if (!CONSTANT_P(operands[2]))
        return \"%m0=%m1-%m2\";
      else
        return \"%m0=%1-%H2\";

    case 3:
    case 4:
      return \"%m0=%m1-%m2\";
    }
}")

(define_expand "subhf3"
  [(set (match_operand:HF 0 "register_operand" "")
	(minus:HF (match_operand:HF 1 "register_operand" "")
		 (match_operand:HF 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (!dsp16xx_subhf3_libcall)
    dsp16xx_subhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, SUBHF3_LIBCALL);
  
  emit_library_call (dsp16xx_subhf3_libcall, 1, HFmode, 2,
		     operands[1], HFmode,
		     operands[2], HFmode);
  emit_move_insn (operands[0], hard_libcall_value(HFmode));
  DONE;
}")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=A")
        (neg:HI (match_operand:HI 1 "register_operand" "A")))]
  ""
  "%0=-%1"
  [(set_attr "type" "special")])

(define_expand "neghf2"
  [(set (match_operand:HF 0 "general_operand" "")
	(neg:HF (match_operand:HF 1 "general_operand" "")))]
  ""
"
{
  if (!dsp16xx_neghf2_libcall)
    dsp16xx_neghf2_libcall = gen_rtx_SYMBOL_REF (Pmode, NEGHF2_LIBCALL);
  
  emit_library_call (dsp16xx_neghf2_libcall, 1, HFmode, 1,
		     operands[1], HFmode);
  emit_move_insn (operands[0], hard_libcall_value(HFmode));
  DONE;
}")



;;
;;  ....................
;;
;;  Multiply instructions
;;

(define_expand "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(mult:HI (match_operand:HI 1 "register_operand" "")
		 (match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "