dsp16xx.h

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/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM

/* Register in which static-chain is passed to a function.  */

#define STATIC_CHAIN_REGNUM 4

/* Register in which address to store a structure value
   is passed to a function.  This is 'r0' in our case */
#define STRUCT_VALUE_REGNUM   REG_R0

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */


enum reg_class 
{ 
    NO_REGS, 
    A0H_REG,
    A0L_REG,
    A0_REG,
    A1H_REG,
    ACCUM_HIGH_REGS,
    A1L_REG,
    ACCUM_LOW_REGS, 
    A1_REG,
    ACCUM_REGS, 
    X_REG, 
    X_OR_ACCUM_LOW_REGS,
    X_OR_ACCUM_REGS,
    YH_REG,
    YH_OR_ACCUM_HIGH_REGS,
    X_OR_YH_REGS,
    YL_REG,
    YL_OR_ACCUM_LOW_REGS,
    X_OR_YL_REGS,
    X_OR_Y_REGS,
    Y_REG,
    ACCUM_OR_Y_REGS,
    PH_REG,
    X_OR_PH_REGS, 
    PL_REG, 
    PL_OR_ACCUM_LOW_REGS,
    X_OR_PL_REGS,
    YL_OR_PL_OR_ACCUM_LOW_REGS,
    P_REG,
    ACCUM_OR_P_REGS,
    YL_OR_P_REGS,
    ACCUM_LOW_OR_YL_OR_P_REGS,
    Y_OR_P_REGS,
    ACCUM_Y_OR_P_REGS, 
    NO_FRAME_Y_ADDR_REGS,
    Y_ADDR_REGS, 
    ACCUM_LOW_OR_Y_ADDR_REGS,
    ACCUM_OR_Y_ADDR_REGS,
    X_OR_Y_ADDR_REGS,
    Y_OR_Y_ADDR_REGS,
    P_OR_Y_ADDR_REGS,
    NON_HIGH_YBASE_ELIGIBLE_REGS,
    YBASE_ELIGIBLE_REGS,
    J_REG,
    J_OR_DAU_16_BIT_REGS,
    BMU_REGS, 
    NOHIGH_NON_ADDR_REGS,
    NON_ADDR_REGS,
    SLOW_MEM_LOAD_REGS,
    NOHIGH_NON_YBASE_REGS,
    NO_ACCUM_NON_YBASE_REGS,
    NON_YBASE_REGS,
    YBASE_VIRT_REGS,
    ACCUM_LOW_OR_YBASE_REGS,
    ACCUM_OR_YBASE_REGS,
    X_OR_YBASE_REGS,
    Y_OR_YBASE_REGS,
    ACCUM_LOW_YL_PL_OR_YBASE_REGS,
    P_OR_YBASE_REGS,
    ACCUM_Y_P_OR_YBASE_REGS,
    Y_ADDR_OR_YBASE_REGS,
    YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS,
    YBASE_OR_YBASE_ELIGIBLE_REGS,
    NO_HIGH_ALL_REGS,
    ALL_REGS, 
    LIM_REG_CLASSES 
};

/* GENERAL_REGS must be the name of a register class */
#define GENERAL_REGS ALL_REGS

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES        \
{                              \
    "NO_REGS",                 \
    "A0H_REG",                 \
    "A0L_REG",                 \
    "A0_REG",                  \
    "A1H_REG",                 \
    "ACCUM_HIGH_REGS",         \
    "A1L_REG",                 \
    "ACCUM_LOW_REGS",          \
    "A1_REG",                  \
    "ACCUM_REGS",              \
    "X_REG",                   \
    "X_OR_ACCUM_LOW_REGS",     \
    "X_OR_ACCUM_REGS",         \
    "YH_REG",                  \
    "YH_OR_ACCUM_HIGH_REGS",   \
    "X_OR_YH_REGS",            \
    "YL_REG",                  \
    "YL_OR_ACCUM_LOW_REGS",    \
    "X_OR_YL_REGS",            \
    "X_OR_Y_REGS",             \
    "Y_REG",                   \
    "ACCUM_OR_Y_REGS",         \
    "PH_REG",                  \
    "X_OR_PH_REGS",            \
    "PL_REG",                  \
    "PL_OR_ACCUM_LOW_REGS",    \
    "X_OR_PL_REGS",            \
    "PL_OR_YL_OR_ACCUM_LOW_REGS", \
    "P_REG",                   \
    "ACCUM_OR_P_REGS",         \
    "YL_OR_P_REGS",            \
    "ACCUM_LOW_OR_YL_OR_P_REGS", \
    "Y_OR_P_REGS",             \
    "ACCUM_Y_OR_P_REGS",       \
    "NO_FRAME_Y_ADDR_REGS",      \
    "Y_ADDR_REGS",               \
    "ACCUM_LOW_OR_Y_ADDR_REGS",  \
    "ACCUM_OR_Y_ADDR_REGS",    \
    "X_OR_Y_ADDR_REGS",        \
    "Y_OR_Y_ADDR_REGS",        \
    "P_OR_Y_ADDR_REGS",        \
    "NON_HIGH_YBASE_ELIGIBLE_REGS", \
    "YBASE_ELIGIBLE_REGS",     \
    "J_REG",                   \
    "J_OR_DAU_16_BIT_REGS",    \
    "BMU_REGS",                \
    "NOHIGH_NON_ADDR_REGS",    \
    "NON_ADDR_REGS",           \
    "SLOW_MEM_LOAD_REGS",      \
    "NOHIGH_NON_YBASE_REGS",   \
    "NO_ACCUM_NON_YBASE_REGS", \
    "NON_YBASE_REGS",          \
    "YBASE_VIRT_REGS",         \
    "ACCUM_LOW_OR_YBASE_REGS", \
    "ACCUM_OR_YBASE_REGS",     \
    "X_OR_YBASE_REGS",         \
    "Y_OR_YBASE_REGS",         \
    "ACCUM_LOW_YL_PL_OR_YBASE_REGS", \
    "P_OR_YBASE_REGS",         \
    "ACCUM_Y_P_OR_YBASE_REGS", \
    "Y_ADDR_OR_YBASE_REGS",    \
    "YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS", \
    "YBASE_OR_YBASE_ELIGIBLE_REGS", \
    "NO_HIGH_ALL_REGS",        \
    "ALL_REGS"                 \
}

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS   \
{                            \
    {0x00000000,  0x00000000},      /* no reg */                             \
    {0x00000001,  0x00000000},      /* a0h */                                \
    {0x00000002,  0x00000000},      /* a0l */                                \
    {0x00000003,  0x00000000},      /* a0h:a0l */                            \
    {0x00000004,  0x00000000},      /* a1h */                                \
    {0x00000005,  0x00000000},      /* accum high */                         \
    {0x00000008,  0x00000000},      /* a1l */                                \
    {0x0000000A,  0x00000000},      /* accum low */                          \
    {0x0000000c,  0x00000000},      /* a1h:a1l */                            \
    {0x0000000f,  0x00000000},      /* accum regs */                         \
    {0x00000010,  0x00000000},      /* x reg */                              \
    {0x0000001A,  0x00000000},      /* x & accum_low_regs */                 \
    {0x0000001f,  0x00000000},      /* x & accum regs */                     \
    {0x00000020,  0x00000000},      /* y high */                             \
    {0x00000025,  0x00000000},      /* yh, accum high */                     \
    {0x00000030,  0x00000000},      /* x & yh */                             \
    {0x00000040,  0x00000000},      /* y low */                              \
    {0x0000004A,  0x00000000},      /* y low, accum_low */                   \
    {0x00000050,  0x00000000},      /* x & yl */                             \
    {0x00000060,  0x00000000},      /* yl:yh */                              \
    {0x00000070,  0x00000000},      /* x, yh,a nd yl */                      \
    {0x0000006F,  0x00000000},      /* accum, y */                           \
    {0x00000080,  0x00000000},      /* p high */                             \
    {0x00000090,  0x00000000},      /* x & ph */                             \
    {0x00000100,  0x00000000},      /* p low */                              \
    {0x0000010A,  0x00000000},      /* p_low and accum_low */                \
    {0x00000110,  0x00000000},      /* x & pl */                             \
    {0x0000014A,  0x00000000},      /* pl,yl,a1l,a0l */                      \
    {0x00000180,  0x00000000},      /* pl:ph */                              \
    {0x0000018F,  0x00000000},      /* accum, p */                           \
    {0x000001C0,  0x00000000},      /* pl:ph and yl */                       \
    {0x000001CA,  0x00000000},      /* pl:ph, yl, a0l, a1l */                \
    {0x000001E0,  0x00000000},      /* y or p */                             \
    {0x000001EF,  0x00000000},      /* accum, y or p */                      \
    {0x00000E00,  0x00000000},      /* r0-r2 */                              \
    {0x00001E00,  0x00000000},      /* r0-r3 */                              \
    {0x00001E0A,  0x00000000},      /* r0-r3, accum_low */                   \
    {0x00001E0F,  0x00000000},      /* accum,r0-r3 */                        \
    {0x00001E10,  0x00000000},      /* x,r0-r3 */                            \
    {0x00001E60,  0x00000000},      /* y,r0-r3 */                            \
    {0x00001F80,  0x00000000},      /* p,r0-r3 */                            \
    {0x00001FDA,  0x00000000},      /* ph:pl, r0-r3, x,a0l,a1l */            \
    {0x00001fff,  0x00000000},      /* accum,x,y,p,r0-r3 */                  \
    {0x00002000,  0x00000000},      /* j */                                  \
    {0x00002025,  0x00000000},      /* j, yh, a1h, a0h */                    \
    {0x001E0000,  0x00000000},      /* ar0-ar3 */                            \
    {0x03FFE1DA,  0x00000000},      /* non_addr except yh,a0h,a1h */         \
    {0x03FFE1FF,  0x00000000},      /* non_addr regs */                      \
    {0x03FFFF8F,  0x00000000},      /* non ybase except yh, yl, and x */     \
    {0x03FFFFDA,  0x00000000},      /* non ybase regs except yh,a0h,a1h */   \
    {0x03FFFFF0,  0x00000000},      /* non ybase except a0,a0l,a1,a1l */     \
    {0x03FFFFFF,  0x00000000},      /* non ybase regs */                     \
    {0xFC000000,  0x03FFFFFF},      /* virt ybase regs */                    \
    {0xFC00000A,  0x03FFFFFF},      /* accum_low, virt ybase regs */         \
    {0xFC00000F,  0x03FFFFFF},      /* accum, virt ybase regs */             \
    {0xFC000010,  0x03FFFFFF},      /* x,virt ybase regs */                  \
    {0xFC000060,  0x03FFFFFF},      /* y,virt ybase regs */                  \
    {0xFC00014A,  0x03FFFFFF},      /* accum_low, yl, pl, ybase */           \
    {0xFC000180,  0x03FFFFFF},      /* p,virt ybase regs */                  \
    {0xFC0001EF,  0x03FFFFFF},      /* accum,y,p,ybase regs */               \
    {0xFC001E00,  0x03FFFFFF},      /* r0-r3, ybase regs */                  \
    {0xFC001FDA,  0x03FFFFFF},      /* r0-r3, pl:ph,yl,x,a1l,a0l */          \
    {0xFC001FFF,  0x03FFFFFF},      /* virt ybase, ybase eligible regs */    \
    {0xFCFFFFDA,  0x03FFFFFF},      /* all regs except yh,a0h,a1h */         \
    {0xFFFFFFFF,  0x03FFFFFF}       /* all regs */                           \
}


/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

#define REGNO_REG_CLASS(REGNO) regno_reg_class(REGNO)

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS NO_REGS
#define BASE_REG_CLASS  Y_ADDR_REGS

/* Get reg_class from a letter such as appears in the machine description. */

#define REG_CLASS_FROM_LETTER(C) \
  dsp16xx_reg_class_from_letter(C)

#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X)  \
   secondary_reload_class(CLASS, MODE, X)

/* When defined, the compiler allows registers explicitly used in the
   rtl to be used as spill registers but prevents the compiler from
   extending the lifetime of these registers. */

#define SMALL_REGISTER_CLASSES 1

/* Macros to check register numbers against specific register classes.  */

/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

/* A C expression which is nonzero if register REGNO is suitable for use
   as a base register in operand addresses. It may be either a suitable
   hard register or a pseudo register that has been allocated such a
   hard register. 

  On the 1610 the Y address pointers can be used as a base registers */
#define REGNO_OK_FOR_BASE_P(REGNO) \
(((REGNO) >= REG_R0 && (REGNO) < REG_R3 + 1) || ((unsigned) reg_renumber[REGNO] >= REG_R0  \
                                   && (unsigned) reg_renumber[REGNO] < REG_R3 + 1))

#define REGNO_OK_FOR_YBASE_P(REGNO) \
  (((REGNO) == REG_YBASE) || ((unsigned) reg_renumber[REGNO] == REG_YBASE))

#define REGNO_OK_FOR_INDEX_P(REGNO)  0

#ifdef ALL_16_BIT_REGISTERS
#define IS_32_BIT_REG(REGNO)  0
#else
#define IS_32_BIT_REG(REGNO)     \
  ((REGNO) == REG_A0 || (REGNO) == REG_A1 || (REGNO) == REG_Y || (REGNO) == REG_PROD)
#endif

/* Given an rtx X being reloaded into a reg required to be
   in class CLASS, return the class of reg to actually use.
   In general this is just CLASS; but on some machines
   in some cases it is preferable to use a more restrictive class.
   Also, we must ensure that a PLUS is reloaded either
   into an accumulator or an address register.  */

#define PREFERRED_RELOAD_CLASS(X,CLASS)	 preferred_reload_class (X, CLASS)

/*   A C expression that places additional restrictions on the register
     class to use when it is necessary to be able to hold a value of
     mode MODE in a reload register for which class CLASS would
     ordinarily be used.

     Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when
     there are certain modes that simply can't go in certain reload
     classes.

     The value is a register class; perhaps CLASS, or perhaps another,
     smaller class.

     Don't define this macro unless the target machine has limitations