dsp16xx.h

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   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 16

/* Maximum number of bits in a word. */
#define MAX_BITS_PER_WORD 16

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 1

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 16

/* Allocation boundary (in *bits*) for storing pointers in memory.  */
#define POINTER_BOUNDARY 16

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 16

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 16

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Biggest alignment that any data type can require on this machine, in bits.  */
#define BIGGEST_ALIGNMENT 16

/* Biggest alignment that any structure field can require on this machine, in bits */
#define BIGGEST_FIELD_ALIGNMENT 16

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 16

/* Number of bits which any structure or union's size must be a multiple of. Each structure
   or union's size is rounded up to a multiple of this */
#define STRUCTURE_SIZE_BOUNDARY 16

/* Define this if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT  1

/* An integer expression for the size in bits of the largest integer machine mode that
   should actually be used. All integer machine modes of this size or smaller can be
   used for structures and unions with the appropriate sizes. */
#define MAX_FIXED_MODE_SIZE 32

/* LAYOUT OF SOURCE LANGUAGE DATA TYPES */

#define CHAR_TYPE_SIZE         16
#define SHORT_TYPE_SIZE        16
#define INT_TYPE_SIZE          16
#define LONG_TYPE_SIZE         32
#define LONG_LONG_TYPE_SIZE    32
#define FLOAT_TYPE_SIZE        32
#define DOUBLE_TYPE_SIZE       32
#define LONG_DOUBLE_TYPE_SIZE  32

/* An expression whose value is 1 or 0, according to whether the type char should be
   signed or unsigned by default. */

#define DEFAULT_SIGNED_CHAR 1

/* A C expression to determine whether to give an enum type only as many bytes
   as it takes to represent the range of possible values of that type. A nonzero
   value means to do that; a zero value means all enum types should be allocated
   like int. */

#define DEFAULT_SHORT_ENUMS 0

/* A C expression for a string describing the name of the data type to use for
   size values. */

#define SIZE_TYPE    "long unsigned int"

/* A C expression for a string describing the name of the datat type to use for the
   result of subtracting two pointers */

#define PTRDIFF_TYPE "long int"

#define TARGET_BELL     '\a'
#define TARGET_BS       '\b'
#define TARGET_TAB      '\t'
#define TARGET_NEWLINE  '\n'
#define TARGET_VT       '\v'
#define TARGET_FF       '\f'
#define TARGET_CR       '\r'


/* REGISTER USAGE.  */

#define ALL_16_BIT_REGISTERS  1

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to FIRST_PSEUDO_REGISTER-1 */

#define FIRST_PSEUDO_REGISTER (REG_YBASE31 + 1)

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.

   The registers are laid out as follows:

   {a0,a0l,a1,a1l,x,y,yl,p,pl} - Data Arithmetic Unit
   {r0,r1,r2,r3,j,k,ybase} - Y Space Address Arithmetic Unit
   {pt} - X Space Address Arithmetic Unit
   {ar0,ar1,ar2,ar3} - Bit Manipulation UNit
   {pr} - Return Address Register

   We reserve r2 for the Stack Pointer.
   We specify r3 for the Frame Pointer but allow the compiler
   to omit it when possible since we have so few pointer registers. */

#define REG_A0     0
#define REG_A0L    1
#define REG_A1     2
#define REG_A1L    3 
#define REG_X      4
#define REG_Y      5
#define REG_YL     6
#define REG_PROD   7
#define REG_PRODL  8
#define REG_R0     9
#define REG_R1     10
#define REG_R2     11
#define REG_R3     12
#define REG_J      13
#define REG_K      14
#define REG_YBASE  15
#define REG_PT     16
#define REG_AR0    17
#define REG_AR1    18
#define REG_AR2    19
#define REG_AR3    20
#define REG_C0     21
#define REG_C1     22
#define REG_C2     23
#define REG_PR     24
#define REG_RB     25
#define REG_YBASE0 26
#define REG_YBASE1 27
#define REG_YBASE2 28
#define REG_YBASE3 29
#define REG_YBASE4 30
#define REG_YBASE5 31
#define REG_YBASE6 32
#define REG_YBASE7 33
#define REG_YBASE8 34
#define REG_YBASE9 35
#define REG_YBASE10 36
#define REG_YBASE11 37
#define REG_YBASE12 38
#define REG_YBASE13 39
#define REG_YBASE14 40
#define REG_YBASE15 41
#define REG_YBASE16 42
#define REG_YBASE17 43
#define REG_YBASE18 44
#define REG_YBASE19 45
#define REG_YBASE20 46
#define REG_YBASE21 47
#define REG_YBASE22 48
#define REG_YBASE23 49
#define REG_YBASE24 50
#define REG_YBASE25 51
#define REG_YBASE26 52
#define REG_YBASE27 53
#define REG_YBASE28 54
#define REG_YBASE29 55
#define REG_YBASE30 56
#define REG_YBASE31 57

/* Do we have a accumulator register? */
#define IS_ACCUM_REG(REGNO) ((REGNO) >= REG_A0 && (REGNO) <= REG_A1L)
#define IS_ACCUM_LOW_REG(REGNO) ((REGNO) == REG_A0L || (REGNO) == REG_A1L)

/* Do we have a virtual ybase register */
#define IS_YBASE_REGISTER_WINDOW(REGNO) ((REGNO) >= REG_YBASE0 && (REGNO) <= REG_YBASE31)

#define IS_ADDRESS_REGISTER(REGNO) ((REGNO) >= REG_R0 && (REGNO) <= REG_R3)

#define FIXED_REGISTERS     \
{0, 0, 0, 0, 0, 0, 0, 0, 0, \
 0, 0, 0, 1, 0, 0, 1,       \
 1,                         \
 0, 0, 0, 0,                \
 1, 1, 1,                   \
 0, 0,                      \
 0, 0, 0, 0, 0, 0, 0, 0,    \
 0, 0, 0, 0, 0, 0, 0, 0,    \
 0, 0, 0, 0, 0, 0, 0, 0,    \
 0, 0, 0, 0, 0, 0, 0, 0}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   On the 1610 'a0' holds return values from functions. 'r0' holds
   structure-value addresses.

   In addition we don't save either j, k, ybase or any of the
   bit manipulation registers.  */


#define CALL_USED_REGISTERS   \
{1, 1, 1, 1, 0, 1, 1, 1, 1,   \
 1, 0, 0, 1, 1, 1, 1,         \
 1,                           \
 0, 0, 1, 1,                  \
 1, 1, 1,                     \
 0, 1,                        \
 0, 0, 0, 0, 0, 0, 0, 0,      \
 0, 0, 0, 0, 0, 0, 0, 0,      \
 0, 0, 0, 0, 0, 0, 0, 0,      \
 0, 0, 0, 0, 0, 0, 0, 0}

/* List the order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.

   We allocate in the following order:
 */

#define REG_ALLOC_ORDER					\
{ REG_R0, REG_R1, REG_R2, REG_PROD, REG_Y, REG_X,       \
  REG_PRODL, REG_YL, REG_AR0, REG_AR1,                  \
  REG_RB, REG_A0, REG_A1, REG_A0L,                      \
  REG_A1L, REG_AR2, REG_AR3,                            \
  REG_YBASE, REG_J, REG_K, REG_PR, REG_PT, REG_C0,      \
  REG_C1, REG_C2, REG_R3,				\
  REG_YBASE0, REG_YBASE1, REG_YBASE2, REG_YBASE3,       \
  REG_YBASE4, REG_YBASE5, REG_YBASE6, REG_YBASE7,       \
  REG_YBASE8, REG_YBASE9, REG_YBASE10, REG_YBASE11,     \
  REG_YBASE12, REG_YBASE13, REG_YBASE14, REG_YBASE15,   \
  REG_YBASE16, REG_YBASE17, REG_YBASE18, REG_YBASE19,   \
  REG_YBASE20, REG_YBASE21, REG_YBASE22, REG_YBASE23,   \
  REG_YBASE24, REG_YBASE25, REG_YBASE26, REG_YBASE27,   \
  REG_YBASE28, REG_YBASE29, REG_YBASE30, REG_YBASE31 }

/* Zero or more C statements that may conditionally modify two
   variables `fixed_regs' and `call_used_regs' (both of type `char
   []') after they have been initialized from the two preceding
   macros.

   This is necessary in case the fixed or call-clobbered registers
   depend on target flags.

   You need not define this macro if it has no work to do.

   If the usage of an entire class of registers depends on the target
   flags, you may indicate this to GCC by using this macro to modify
   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
   the classes which should not be used by GCC.  Also define the macro
   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
   letter for a class that shouldn't be used.

   (However, if this class is not included in `GENERAL_REGS' and all
   of the insn patterns whose constraints permit this class are
   controlled by target switches, then GCC will automatically avoid
   using these registers when the target switches are opposed to
   them.)  If the user tells us there is no BMU, we can't use
   ar0-ar3 for register allocation */

#define CONDITIONAL_REGISTER_USAGE					\
do									\
  {									\
    if (!TARGET_BMU)						        \
      {									\
	int regno;							\
									\
	for (regno = REG_AR0; regno <= REG_AR3; regno++)	        \
	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
      }									\
    if (TARGET_RESERVE_YBASE)						\
      {									\
	int regno;							\
									\
	for (regno = REG_YBASE0; regno <= REG_YBASE31; regno++)	        \
	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
      }									\
  }									\
while (0)

/* Determine which register classes are very likely used by spill registers.
   local-alloc.c won't allocate pseudos that have these classes as their
   preferred class unless they are "preferred or nothing".  */

#define CLASS_LIKELY_SPILLED_P(CLASS) \
 ((CLASS) != ALL_REGS && (CLASS) != YBASE_VIRT_REGS)

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers. */

#define HARD_REGNO_NREGS(REGNO, MODE)                                 \
  (GET_MODE_SIZE(MODE))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */

#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok(REGNO, MODE)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)		     \
  (((MODE1) == (MODE2)) ||                           \
   (GET_MODE_CLASS((MODE1)) == MODE_FLOAT)           \
    == (GET_MODE_CLASS((MODE2)) == MODE_FLOAT))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* DSP1600 pc isn't overloaded on a register.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  
   This is r3 in our case */
#define STACK_POINTER_REGNUM  REG_R3

/* Base register for access to local variables of the function.
   This is r2 in our case   */
#define FRAME_POINTER_REGNUM  REG_R2

/* We can debug without the frame pointer */
#define CAN_DEBUG_WITHOUT_FP 1

/* The 1610 saves the return address in this register */
#define RETURN_ADDRESS_REGNUM REG_PR