1750a.md

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  "*
    switch (which_alternative)
      {
        case 0:
          return \"aisp r%0,%2\";
        case 1:
          return \"sisp r%0,%J2\";
        case 2:
          if (INTVAL(operands[2]) < 0)
            return \"sim r%0,%J2\";
          else
            return \"aim r%0,%2\";
        case 3:
          return \"ar r%0,r%2\";
        case 4:
          return \"a r%0,%2\";
        case 5:
          return \"incm %2,%0\";
        case 6:
          return \"decm %J2,%0\";
      } ")

;; double integer
(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    dar r%0,r%2
    da  r%0,%2 ")

(define_insn "addhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
                 (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    far r%0,r%2
    fa  r%0,%2 ")

(define_insn "addtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
                 (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    efar r%0,r%2
    efa  r%0,%2 ")


;; subtract instructions

;; single integer
(define_insn "subqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
        (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
                  (match_operand:QI 2 "general_operand"  "I,i,r,m,I")))]
  ""
  "@
    sisp r%0,%2
    sim  r%0,%2
    sr   r%0,r%2
    s    r%0,%2
    decm %2,%0 ")

;; double integer
(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (minus:HI (match_operand:HI 1 "register_operand" "0,0")
                  (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    dsr r%0,r%2
    ds  r%0,%2 ")

(define_insn "subhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (minus:HF (match_operand:HF 1 "register_operand" "0,0")
                  (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    fsr r%0,r%2
    fs  r%0,%2 ")

(define_insn "subtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
                  (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    efsr r%0,r%2
    efs  r%0,%2 ")


;; multiply instructions

(define_insn "mulqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
        (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
                 (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))]
  ""
  "@
     misp r%0,%2
     misn r%0,%J2
     msim r%0,%2
     msr  r%0,r%2
     ms   r%0,%2  ")


; 32-bit product
(define_insn "mulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
    (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r"))
             (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))]
  ""
  "*
    if (REGNO (operands[1]) != REGNO (operands[0]))
      output_asm_insn (\"lr r%0,r%1\", operands);

    switch (which_alternative)
      {
      case 0:
        return \"mr  r%0,r%2\";
      case 1:
        return \"m   r%0,%2\";
      case 2:
        return \"mim r%0,%2\";
      }
  ")


(define_insn "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    dmr r%0,r%2
    dm  r%0,%2 ")

; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)

(define_insn "mulhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
                 (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    fmr r%0,r%2
    fm  r%0,%2 ")

(define_insn "multqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
                 (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    efmr r%0,r%2
    efm  r%0,%2 ")


;; divide instructions
;; The 1750 16bit integer division instructions deliver a 16-bit
;; quotient and a 16-bit remainder, where the remainder is in the next higher
;; register number above the quotient. For now, we haven't found a way
;; to give the reload pass knowledge of this property. So we make do with
;; whatever registers the allocator wants, and willy-nilly output a pair of
;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
;; A comment in the description of `divmodM4' suggests that one leave the divM3
;; undefined when there is a divmodM4 available.

(define_insn "divmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
        (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
                (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))
   (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
        (mod:QI (match_dup 1) (match_dup 2)))]
  ""
  "*
   {
     char *istr;
     switch(which_alternative)
       {
       case 0:
         istr = \"disp\";
         break;
       case 1:
	 {
	   rtx new_opnds[4];
	   new_opnds[0] = operands[0];
	   new_opnds[1] = operands[1];
	   new_opnds[2] = GEN_INT (-INTVAL(operands[2]));
	   new_opnds[3] = operands[3];
           istr = \"disn\";
	   return mod_regno_adjust (istr, new_opnds);
	 }
         break;
       case 2:
         istr = \"dvim\";
         break;
       case 3:
         istr = \"dvr \";
         break;
       case 4:
         istr = \"dv  \";
         break;
      }
      return mod_regno_adjust (istr, operands);
     }")

;; Division for other types is straightforward.

(define_insn "divhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (div:HI (match_operand:HI 1 "register_operand" "0,0")
                (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    ddr r%0,r%2
    dd  r%0,%2 ")

(define_insn "divhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (div:HF (match_operand:HF 1 "register_operand" "0,0")
                (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    fdr r%0,r%2
    fd  r%0,%2 ")

(define_insn "divtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
                (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    efdr r%0,r%2
    efd  r%0,%2 ")


;; Other arithmetic instructions:

;; Absolute value

(define_insn "absqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (abs:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "abs r%0,r%1")

(define_insn "abshi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (abs:HI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "dabs r%0,r%1")

(define_insn "abshf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (abs:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "fabs r%0,r%1")


;; Negation

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (neg:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "neg r%0,r%1")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (neg:HI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "dneg r%0,r%1")

(define_insn "neghf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (neg:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "fneg r%0,r%1")

; The 1750A does not have an extended float negate instruction, so simulate.
(define_expand "negtqf2"
  [(set (match_operand:TQF 0 "register_operand" "=&r")
        (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
  ""
  "
   emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
   emit_insn(gen_rtx(SET,VOIDmode,operands[0],
             gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
   DONE;
  ")


;; bit-logical instructions

;; Set Bit
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r,m")
        (ior:QI  (match_operand:QI 1 "general_operand" "0,0")
                 (match_operand:QI 2 "const_int_operand" "i,i")))]
  "one_bit_set_p (INTVAL (operands [2]))"
  "@
    sbr    %b2,r%0
    sb     %b2,%0")

;; Reset Bit
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r,m")
        (and:QI  (match_operand:QI 1 "general_operand" "0,0")
                 (match_operand:QI 2 "const_int_operand" "i,i")))]
  "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)"
  "@
    rbr    %B2,r%0
    rb     %B2,%0")

;; Set Variable Bit
(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
        (ior:QI  (match_operand:QI 1 "register_operand" "0")
                 (lshiftrt:QI (const_int 0x8000)
                      (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "svbr   r%2,%r0")

;; Reset Variable Bit
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r")
        (and:QI  (match_operand:QI 1 "general_operand" "0")
            (not:QI (lshiftrt:QI (const_int 0x8000)
                        (match_operand:QI 2 "register_operand" "r")))))]
  ""
  "rvbr   r%2,%r0")


;; AND

(define_insn "andqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
        (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
                (match_operand:QI 2 "general_operand" "M,r,m")))]
  ""
  "@
    andm r%0,%2
    andr r%0,r%2
    and  r%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "andhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (and:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "danr.m %0,%2")

;; OR

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
        (ior:QI  (match_operand:QI 1 "general_operand" "%0,0,0")
                 (match_operand:QI 2 "general_operand" "M,r,m")))]
  ""
  "@
    orim r%0,%2
    orr  r%0,r%2
    or   r%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (ior:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "dorr.m %0,%2")

;; XOR

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
                (match_operand:QI 2 "general_operand"  "M,r,m")))]
  ""
  "@
    xorm r%0,%2
    xorr r%0,r%2
    xor  r%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (xor:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "dxrr.m %0,%2")

;; NAND

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
	(ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
		(not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
  ""
  "@
    nim r%0,%2
    nr  r%0,r%2
    n   r%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
		(not:HI (match_operand:HI 2 "register_operand" "r"))))]
  ""
  "dnr.m %0,%2")

;; NOT

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (not:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "nr r%0,r%0")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (not:HI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "dnr.m %0,%0")


;; Shift instructions

; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
  ""
  "@
    sll r%0,%2
    slr r%0,r%2 ")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "nonmemory_operand" "L,r")))]
  ""                        ; the 'L' constraint is a slight imprecise...
  "*
    if (which_alternative == 1)
      return \"dslr r%0,r%2\";
    else if (INTVAL(operands[2]) <= 16)
      return \"dsll r%0,%2\";
    else
      {
        output_asm_insn (\"dsll r%0,16  ; ashlhi3 shiftcnt > 16\", operands);
        return \"sll r%0,%w2\";
      }
  ")


;; Right shift by a variable shiftcount works by negating the shift count,
;; then emitting a right shift with the shift count negated.  This means
;; that all actual shift counts in the RTL will be positive.  This 
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
;; which isn't valid.
(define_expand "lshrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
		     (match_operand:QI 2 "nonmemory_operand" "g")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")