1750a.md

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;;- Machine description for GNU compiler
;;- MIL-STD-1750A version.
;; Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
;; Contributed by O.M.Kellogg, DASA ([e-mail]).

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 1, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;;- instruction definitions

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;- When naming insn's (operand 0 of define_insn) be careful about using
;;- names from other targets machine descriptions.

;; MIL-STD-1750 specific remarks:
;;
;; 1) BITS_PER_UNIT = 16
;;
;; 2) GCC   to    MIL-STD-1750       data type mappings:
;;    QImode => single integer (16 bits or 1 reg).
;;    HImode => double integer (32 bits or 2 regs).
;;    HFmode => single precision float (32 bits or 2 regs).
;;    TQFmode => extended precision float (48 bits or 3 regs).
;; 
;; 3) Immediate integer operands Constraints:
;;    'I'  1 .. 16
;;    'J' -1 ..-16
;;    'K'  0 .. 15
;;    'L'  0 .. 255
;;    'M' -32768 .. 32767
;;    'O' => 0  (for optimizations and GCC quirks)
;;
;; Further notes:
;;-  Assembly output ending in ".M" are macros in file M1750.INC


;; stackpush
(define_insn ""
  [(set (match_operand:QI 0 "push_operand" "=<")
        (match_operand:QI 1 "general_operand" "r"))]
  ""
  "pshm r%1,r%1")

(define_insn ""
  [(set (match_operand:HI 0 "push_operand" "=<")
        (match_operand:HI 1 "general_operand" "r"))]
  ""
  "pshm r%1,r%d1")

(define_insn ""
  [(set (match_operand:HF 0 "push_operand" "=<")
        (match_operand:HF 1 "general_operand" "r"))]
  ""
  "pshm r%1,r%d1")

(define_insn ""
  [(set (match_operand:TQF 0 "push_operand" "=<")
        (match_operand:TQF 1 "general_operand" "r"))]
  ""
  "pshm r%1,r%t1")

;; stackpop
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r")
        (match_operand:QI 1 "push_operand" ">"))]
  ""
  "popm r%1,r%1")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r")
        (match_operand:HI 1 "push_operand" ">"))]
  ""
  "popm r%1,r%d1")

(define_insn ""
  [(set (match_operand:HF 0 "general_operand" "=r")
        (match_operand:HF 1 "push_operand" ">"))]
  ""
  "popm r%1,r%d1")
   
(define_insn ""
  [(set (match_operand:TQF 0 "general_operand" "=r")
        (match_operand:TQF 1 "push_operand" ">"))]
  ""
  "popm r%1,r%t1")


;; Test operations.

(define_insn "tstqi"
  [(set (cc0)
        (match_operand:QI 0 "register_operand" "r"))]
  ""
  "lr r%0,r%0   ; from tstqi")

(define_insn "tsthi"
  [(set (cc0)
        (match_operand:HI 0 "register_operand" "r"))]
  ""
  "dlr r%0,r%0   ; from tsthi")

; With 1750A floats, testing the most significant word suffices.

(define_insn "tsthf"
  [(set (cc0)
        (match_operand:HF 0 "register_operand" "r"))]
  ""
  "lr r%0,r%0   ; tsthf")

(define_insn "tsttqf"
  [(set (cc0)
        (match_operand:TQF 0 "register_operand" "r"))]
  ""
  "lr r%0,r%0   ; tsttqf")


;; block move.

(define_insn "movstrqi"
  [(set (match_operand:BLK 0 "mov_memory_operand" "m")
	(match_operand:BLK 1 "mov_memory_operand" "m"))
   (use (match_operand:QI 2 "general_operand" "r"))
   (match_operand 3 "" "")
   (clobber (match_dup 0))
   (clobber (match_dup 1))
   (clobber (match_dup 2))]
  ""
  "*
   {
     rtx regops[3];

     regops[0] = XEXP (operands[0], 0);
     regops[1] = XEXP (operands[1], 0);
     regops[2] = operands[2];

     return movcnt_regno_adjust (regops);
   } ")


;; compare instructions.

(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
                 (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
  ""
  "*
   {
     if (next_cc_user_is_unsigned (insn))
       switch (which_alternative)
	 {
	 case 0:
	 case 1:
	 case 2:
	   return \"ucim.m %0,%1\";
	 case 3:
	   return \"ucr.m %0,%1\";
	 case 4:
	   return \"uc.m %0,%1\";
	 }
     else
       switch (which_alternative)
	 {
	 case 0:
	   return \"cisp r%0,%1\";
	 case 1:
	   return \"cisn r%0,%J1\";
	 case 2:
	   return \"cim  r%0,%1\";
	 case 3:
	   return \"cr   r%0,r%1\";
	 case 4:
	   return \"c    r%0,%1\";
	 }
   } ")

(define_insn "cmphi"
  [(set (cc0)
        (compare (match_operand:HI 0 "general_operand" "r,r")
                 (match_operand:HI 1 "general_operand" "r,m")))]
  ""
  "*
   {
     if (next_cc_user_is_unsigned (insn))
       {
         if (which_alternative == 0)
	   return \"ducr.m %0,%1\";
	 return \"duc.m %0,%1\";
       }
     else
       {
         if (which_alternative == 0)
           return \"dcr r%0,r%1\";
         return \"dc  r%0,%1\";
       }
   } ")

(define_insn "cmphf"
 [(set (cc0)
       (compare (match_operand:HF 0 "general_operand" "r,r")
                (match_operand:HF 1 "general_operand" "r,m")))]
 ""
 "@
   fcr r%0,r%1
   fc  r%0,%1 ")

(define_insn "cmptqf"
  [(set (cc0)
        (compare (match_operand:TQF 0 "general_operand" "r,r")
                 (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
    efcr r%0,r%1
    efc  r%0,%1 ")


;; truncation instructions
;;- 1750: any needed?

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "lr  r%0,r%d1")


;; zero extension instructions: not defined, GCC can synthesize

;; sign extension instructions

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )]
  ""
  "*
    if (which_alternative == 0)
      {
        if (REGNO (operands [0]) != REGNO (operands [1]))
          output_asm_insn (\"lr r%0,r%1\", operands);
      }
    else
      output_asm_insn (\"l  r%0,%1\", operands);
    return \"dsra r%0,16  ;extendqihi2\";
  ")


;; Conversions between float and double.

; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
(define_insn "extendhftqf2"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
  ""
  "*
    output_asm_insn(\"xorr r%t0,r%t0   ;extendhftqf2\", operands);
    if (which_alternative == 0)
      {
        if (REGNO (operands[1]) != REGNO (operands[0]))
          return \"dlr r%0,r%1\";
        else
          return \";\";
      }
    else
      return \"dl  r%0,%1\";
   ")

; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
(define_insn "trunctqfhf2"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (float_truncate:HF
          (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
     dlr r%0,r%1  ;trunctqfhf2
     dl  r%0,%1   ;trunctqfhf2 ")


;; Conversion between fixed point and floating point.

(define_insn "floatqihf2"
  [(set           (match_operand:HF 0 "register_operand" "=r")
        (float:HF (match_operand:QI 1 "register_operand" "r")))]
  ""
  "flt r%0,r%1")

(define_insn "floathitqf2"
  [(set           (match_operand:TQF 0 "register_operand" "=r")
        (float:TQF (match_operand:HI 1 "register_operand" "r")))]
  ""
  "eflt r%0,r%1")


;; Convert floats to ints

(define_insn "fix_trunchfqi2"
  [(set                 (match_operand:QI 0 "register_operand" "=r")
        (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
  ""
  "fix r%0,r%1")

(define_insn "fix_trunctqfhi2"
  [(set                 (match_operand:HI 0 "register_operand" "=r")
        (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
  ""
  "efix r%0,r%1")


;; Move instructions

;; We can't deal with normal byte-size characters, only with WIDE characters!
;; This may appear as a serious restriction, but it also opens the doors
;; for ISO 10646  :-)

;; 16-bit moves

; memory indirect to reg
(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
        (mem:QI (match_operand 1 "memory_operand"  "m")))]
  ""
  "li   r%0,%1")

; reg/const to memory indirect
(define_insn ""
  [(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
        (match_operand:QI 1 "nonmemory_operand"  "r,K"))]
  ""
  "@
     sti  r%1,%0
     stci %1,%0")

; general case
(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
        (match_operand:QI 1 "general_operand"  "O,I,J,i,r,m,r,K"))]
  ""
  "@
     xorr r%0,r%0
     lisp r%0,%1
     lisn r%0,%J1
     lim  r%0,%1
     lr   r%0,r%1
     l    r%0,%1
     st   r%1,%0
     stc  %1,%0   ")

;; 32-bit moves

; memory indirect to reg
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
        (mem:HI (match_operand 1 "memory_operand"  "m")))]
  ""
  "dli  r%0,%1")

; reg to memory indirect
(define_insn ""
  [(set (mem:HI (match_operand 0 "memory_operand" "=m"))
        (match_operand:HI 1 "register_operand"  "r"))]
  ""
  "dsti r%1,%0")

; general case
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
        (match_operand:HI 1 "general_operand"  "O,I,J,r,m,r,K"))]
  ""
  "@
    xorr r%0,r%0\;xorr r%d0,r%d0
    xorr r%0,r%0\;lisp r%d0,%1
    lisn r%0,1  \;lisn r%d0,%J1
    dlr  r%0,r%1
    dl   r%0,%1
    dst  r%1,%0
    stc  0,%0   \;stc  %1,%A0 ")

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "=g")
        (match_operand:HI 1 "general_operand"  "g"))]
  ""
  "
   {
     rtx op1 = operands[1];
     if (GET_CODE (operands[0]) == MEM)
       {
         if (GET_CODE (op1) == MEM
	     || (GET_CODE (op1) == CONST_INT
		 && (INTVAL (op1) < 0 || INTVAL (op1) > 15)))
	   operands[1] = force_reg (HImode, operands[1]);
       }
     else if (GET_CODE (op1) == CONST_INT
	      && (INTVAL (op1) < -16 || INTVAL (op1) > 16))
       operands[1] = force_const_mem (HImode, operands[1]);
   }")


;; Single-Float moves

(define_insn ""
  [(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
        (match_operand:HF 1 "general_operand"  "r,m,r,G"))]
  ""
  "@
    dlr  r%0,r%1
    dl   r%0,%1
    dst  r%1,%0
    stc  0,%0   \;stc 0,%A0 ")

(define_expand "movhf"
  [(set (match_operand:HF 0 "general_operand" "")
        (match_operand:HF 1 "general_operand" ""))]
  ""
  "
   {
     enum rtx_code op1code = GET_CODE (operands[1]);
     if (GET_CODE (operands[0]) == MEM)
       {
         if (op1code == MEM || (op1code == CONST_DOUBLE
             && !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
	   operands[1] = force_reg (HFmode, operands[1]);
       }
     else if (op1code == CONST_DOUBLE)
       operands[1] = force_const_mem (HFmode, operands[1]);
   }")


;; Longfloat moves

(define_insn ""
  [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
        (match_operand:TQF 1 "general_operand"  "r,m,r"))]
  ""
  "@
    eflr.m %0,%1
    efl  r%0,%1
    efst r%1,%0 ")

(define_expand "movtqf"
  [(set (match_operand:TQF 0 "general_operand" "")
        (match_operand:TQF 1 "general_operand" ""))]
  ""
  "
   {
     enum rtx_code op1code = GET_CODE (operands[1]);
     if (GET_CODE (operands[0]) == MEM)
       {
         if (op1code == MEM || op1code == CONST_DOUBLE)
	   operands[1] = force_reg (TQFmode, operands[1]);
       }
     else if (op1code == CONST_DOUBLE)
       operands[1] = force_const_mem (TQFmode, operands[1]);
   }")


;; add instructions 

;; single integer

(define_insn "addqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
        (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
                 (match_operand:QI 2 "general_operand"  "I,J,i,r,m,I,J")))]
  ""