1750a.h

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/* Definitions of target machine for GNU compiler.
   Copyright (C) 1994, 95-98, 1999 Free Software Foundation, Inc.
   Contributed by O.M.Kellogg, DASA ([e-mail])

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */


/* Names to predefine in the preprocessor for this target machine.  */

/* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES.  */
#define CPP_PREDEFINES ""

/* Print subsidiary information on the compiler version in use.  */
#ifdef IEEE
#define TARGET_VERSION fprintf (stderr, " (1750A, IEEE syntax)");
#else
#define TARGET_VERSION fprintf (stderr, " (MIL-STD-1750A)");
#endif

/* Run-time compilation parameters selecting different hardware subsets.  */

#define TARGET_SWITCHES  \
  { {"vaxc-alignment", 2, "Use VAX-C alignment"}, \
    { "", TARGET_DEFAULT, NULL}}

/* Default target_flags if no switches specified.  */

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 1
#endif

/*****************************************************************************/

/* SPECIAL ADDITION FOR MIL-STD-1750A     by O.M.Kellogg, 15-Apr-1993 */
/* See file aux-output.c for the actual data instances. */
struct datalabel_array {
    char *name;
    char value[14];
    int size;
};
struct jumplabel_array {
    int pc;
    int num;
};
enum section { Init, Normal, Konst, Static };
#define DATALBL_ARRSIZ 256
#define JMPLBL_ARRSIZ  256
#ifndef __datalbl
extern struct datalabel_array datalbl[];
extern struct jumplabel_array jmplbl[];
extern int datalbl_ndx, jmplbl_ndx, label_pending, program_counter;
extern enum section current_section;
extern char *sectname[4];
extern char *float_label();
extern struct rtx_def *function_arg ();
extern char *movcnt_regno_adjust ();
extern char *mod_regno_adjust ();
extern char *branch_or_jump ();
#endif
/*--------------------------------------------------------------------*/

/* target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   Though 1750 actually counts bits in big-endian fashion, the sign bit
   is still the most significant bit, which is leftmost. Therefore leaving
   this little-endian. Adjust short before assembler output when needed:
   e.g. in QImode, a GCC bit n is a 1750 bit (15-n). */
#define BITS_BIG_ENDIAN 0 

/* Define this if most significant byte of a word is the lowest numbered.  */
/* For 1750 we can decide arbitrarily
   since there are no machine instructions for them.  */
#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword value is lowest
   numbered.
   True for 1750. */
#define WORDS_BIG_ENDIAN 1

/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT        16

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD        16

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD       1

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE         16

#define PTRDIFF_TYPE        "int"

/* Type to use for `size_t'. If undefined, uses `long unsigned int'. */
#define SIZE_TYPE           "int"

/* 1750a preliminary
   #define TARGET_FLOAT_FORMAT UNKNOWN_FLOAT_FORMAT
*/

/* Allocation boundary (in *bits*) for storing pointers in memory.  */
#define POINTER_BOUNDARY     16

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
/* 1750: should have had to make this 32 when BITS_PER_WORD is 32. */
#define PARM_BOUNDARY        16

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY       16

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY    16

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 16

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT    16

/* Define this to 1 if move instructions will actually fail to work
   when given unaligned data. */
#define STRICT_ALIGNMENT 0

/* Define number of bits in most basic integer type.
   (If undefined, default is BITS_PER_WORD).
   #define INT_TYPE_SIZE  16  */

/* Define number of bits in short integer type.
   (If undefined, default is half of BITS_PER_WORD). */
#define SHORT_TYPE_SIZE 16

/* Define number of bits in long integer type.
   (If undefined, default is BITS_PER_WORD). */
#define LONG_TYPE_SIZE  32

/* Define number of bits in long long integer type.
   (If undefined, default is twice BITS_PER_WORD). */
/* 1750 PRELIMINARY : no processor support for `long long', therefore
        need to check out the long-long opencodings ! */
#define LONG_LONG_TYPE_SIZE  64

/* Define number of bits in char type.
   (If undefined, default is one fourth of BITS_PER_WORD). */
#define CHAR_TYPE_SIZE  16

/* Define number of bits in float type.
   (If undefined, default is BITS_PER_WORD). */
#define FLOAT_TYPE_SIZE  32

/* Define number of bits in double type.
   (If undefined, default is twice BITS_PER_WORD). */
#define DOUBLE_TYPE_SIZE  48

/*****************************************************************************/

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers. */
#define FIRST_PSEUDO_REGISTER 16

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.
   R15 is the 1750A stack pointer. R14 is the frame pointer. */

#define FIXED_REGISTERS  \
 { 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 1, 1 }

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.
   1750: return value in R0 foll. (depending on size of retval).
   Should be possible to refine this (how many regs are actually used) */

#define CALL_USED_REGISTERS \
 { 1, 1, 1, 1, 1, 1, 1, 1, \
   1, 1, 1, 1, 1, 1, 1, 1 }

/* Order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.  List frame pointer
   late and fixed registers last.  Note that, in general, we prefer
   registers listed in CALL_USED_REGISTERS, keeping the others
   available for storage of persistent values.  */

/* #define REG_ALLOC_ORDER \
   { 2, 0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
 */

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.
   All 1750 registers are one word long. */
#define HARD_REGNO_NREGS(REGNO, MODE)   \
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2)	1

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* 1750A pc isn't overloaded on a register.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 15

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 14

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c. */
#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM 14

/* Define this if successive args to a function occupy decreasing addresses
   on the stack. 
   #define ARGS_GROW_DOWNWARD
*/

/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 13

/* Place in which caller passes the structure value address.
   0 means push the value on the stack like an argument. 
   #define STRUCT_VALUE 0
*/

/* Register in which address to store a structure value
   arrives in the function.  
   #define STRUCT_VALUE_INCOMING 0
*/

/* Register in which address to store a structure value
   is passed to a function.  */
#define STRUCT_VALUE_REGNUM 12

/* Define this to be 1 if all structure return values must be in memory. */
#define DEFAULT_PCC_STRUCT_RETURN 0

/*****************************************************************************/

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

/* 1750 note: The names (BASE_REGS/INDEX_REGS) are used in their *gcc sense*
   (i.e. *opposite* to the MIL-STD-1750A defined meanings). This means that
   R1..R15 are called "base" regs and R12..R15 are "index" regs.
   Index reg mode (in the gcc sense) is not yet implemented (these are the
   1750 "Base with Index Reg" instructions, LBX etc. See 1750.md)

   Here's an example to drive this point home: in "LBX B12,R5"
   B12 shall be called the "index" reg and R5 shall be the "base" reg.
   This naming inversion is due to the GCC defined capabilities of
   "Base" vs. "Index" regs. */

enum reg_class { NO_REGS, R2, R0_1, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLASSES };

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Since GENERAL_REGS is the same class as ALL_REGS,
   don't give it a different class number; just make it an alias. */
#define GENERAL_REGS ALL_REGS

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
 { "NO_REGS", "R2", "R0_1", "INDEX_REGS", "BASE_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.
   1750 "index" (remember, in the *GCC* sense!) regs are R12 through R15. 
   The only 1750 register not usable as BASE_REG is R0. */

#define REG_CLASS_CONTENTS  {0, 0x0004, 0x0003, 0xf000, 0xfffe, 0xffff}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */
#define REGNO_REG_CLASS(REGNO) ((REGNO) == 2 ? R2 : (REGNO) == 0 ? R0_1 : \