a29k.md

gcc编译工具没有什么特别

	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
  "TARGET_29050"
  "sqrt %0,%1,2"
  [(set_attr "type" "dsqrt")])

;; SRA
(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		     (match_operand:QI 2 "srcb_operand" "rn")))]
  ""
  "sra %0,%1,%Q2")

;; SRL
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		     (match_operand:QI 2 "srcb_operand" "rn")))]
  ""
  "srl %0,%1,%Q2")

;; STORE
;;
;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
;; stores on systems with DW not set.
(define_insn ""
  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
			(const_int -4)))
	(match_operand:SI 1 "gpc_reg_operand" "r"))]
  "! TARGET_DW_ENABLE"
  "store 0,1,%1,%0"
  [(set_attr "type" "store")])

(define_insn ""
  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
			(const_int -3)))
	(match_operand:SI 1 "gpc_reg_operand" "r"))]
  "! TARGET_DW_ENABLE"
  "store 0,2,%1,%0"
  [(set_attr "type" "store")])

;; STOREM
(define_expand "store_multiple"
  [(use (match_operand 0 "" ""))
   (use (match_operand 1 "" ""))
   (use (match_operand 2 "" ""))]
  ""
  "
{ rtx pat;

 if (TARGET_NO_STOREM_BUG)
    pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]);
  else
    pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]);

  if (pat)
    emit_insn (pat);
  else
    FAIL;

  DONE;
}")

(define_expand "store_multiple_no_bug"
  [(set (match_dup 4)
	(match_operand:PSI 2 "const_int_operand" ""))
   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
			  (match_operand:SI 1 "" ""))])]
  ""
  "
{
  int regno;
  int count;
  rtx from;
  int i;

  /* Support only storing a constant number of hard registers to memory.  */
  if (GET_CODE (operands[2]) != CONST_INT
      || operands[2] == const1_rtx
      || GET_CODE (operands[0]) != MEM
      || GET_CODE (operands[1]) != REG
      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
    FAIL;

  count = INTVAL (operands[2]);
  regno = REGNO (operands[1]);

  /* CR gets set to the number of registers minus one.  */
  operands[2] = GEN_INT(count - 1);

  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
  from = memory_address (SImode, XEXP (operands[0], 0));
  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
					 gen_rtx (MEM, SImode, from),
					 gen_rtx (REG, SImode, regno));
  operands[4] = gen_reg_rtx (PSImode);
  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);

  for (i = 1; i < count; i++)
    XVECEXP (operands[3], 0, i + 2)
      = gen_rtx (SET, VOIDmode,
		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
		 gen_rtx (REG, SImode, regno + i));
}")

(define_expand "store_multiple_bug"
  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
			  (match_operand:SI 1 "" ""))
		     (use (match_operand:SI 2 "" ""))])]
  ""
  "
{
  int regno;
  int count;
  rtx from;
  int i;

  /* Support only storing a constant number of hard registers to memory.  */
  if (GET_CODE (operands[2]) != CONST_INT
      || operands[2] == const1_rtx
      || GET_CODE (operands[0]) != MEM
      || GET_CODE (operands[1]) != REG
      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
    FAIL;

  count = INTVAL (operands[2]);
  regno = REGNO (operands[1]);

  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
  from = memory_address (SImode, XEXP (operands[0], 0));
  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
					 gen_rtx (MEM, SImode, from),
					 gen_rtx (REG, SImode, regno));
  XVECEXP (operands[3], 0, 1)
    = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode));

  for (i = 1; i < count; i++)
    XVECEXP (operands[3], 0, i + 1)
      = gen_rtx (SET, VOIDmode,
		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
		 gen_rtx (REG, SImode, regno + i));
}")

(define_insn ""
  [(set (match_operand 0 "memory_operand" "=m")
	(match_operand 1 "gpc_reg_operand" "r"))
   (clobber (match_scratch:PSI 2 "=&c"))]
  "!TARGET_NO_STOREM_BUG
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
  "mtsrim cr,%S1\;storem 0,0,%1,%0"
  [(set_attr "type" "multi")])

(define_insn ""
  [(match_parallel 0 "store_multiple_operation"
		   [(set (match_operand:SI 1 "memory_operand" "=m")
			 (match_operand:SI 2 "gpc_reg_operand" "r"))
		    (clobber (match_scratch:PSI 3 "=&c"))])]
  "!TARGET_NO_STOREM_BUG"
  "mtsrim cr,%V0\;storem 0,0,%2,%1"
  [(set_attr "type" "multi")])

(define_insn ""
  [(set (match_operand 0 "memory_operand" "=m")
	(match_operand 1 "gpc_reg_operand" "r"))
   (use (match_operand:PSI 2 "register_operand" "+c"))
   (clobber (match_dup 2))]
  "TARGET_NO_STOREM_BUG
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
  "storem 0,0,%1,%0"
  [(set_attr "type" "store")])

(define_insn ""
  [(match_parallel 0 "store_multiple_operation"
		   [(set (match_operand:SI 1 "memory_operand" "=m")
			 (match_operand:SI 2 "gpc_reg_operand" "r"))
		    (use (match_operand:PSI 3 "register_operand" "+c"))
		    (clobber (match_dup 3))])]
  "TARGET_NO_STOREM_BUG"
  "storem 0,0,%2,%1"
  [(set_attr "type" "store")])

;; SUB
;;
;; Either operand can be a register or an 8-bit constant, but both cannot be
;; constants (can't usually occur anyway).
(define_expand "subsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(minus:SI (match_operand:SI 1 "srcb_operand" "")
		  (match_operand:SI 2 "srcb_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[0]) == CONST_INT
      && GET_CODE (operands[1]) == CONST_INT)
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
		  (match_operand:SI 2 "srcb_operand" "rI,r")))]
  "register_operand (operands[1], SImode)
   || register_operand (operands[2], SImode)"
  "@
   sub %0,%1,%2
   subr %0,%2,%1")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
  ""
  "sub %L0,%L1,%L2\;subc %0,%1,%2"
  [(set_attr "type" "multi")])

;; SUBR (also used above in SUB)
(define_insn "negdi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
  ""
  "subr %L0,%L1,0\;subrc %0,%1,0"
  [(set_attr "type" "multi")])

(define_insn "negsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  ""
  "subr %0,%1,0")

;; XNOR
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
  ""
  "xnor %0,%1,%2")

;; XOR

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
		(match_operand:SI 2 "and_operand" "rI,K")))]
  ""
  "@
   xor %0,%1,%2
   xnor %0,%1,%C2")

;; Can use XOR to negate floating-point values, but we are better off not doing
;; it that way on the 29050 so it can combine with the fmac insns.
(define_expand "negsf2"
  [(parallel [(set (match_operand:SF 0 "register_operand" "")
		   (neg:SF (match_operand:SF 1 "register_operand" "")))
	      (clobber (match_scratch:SI 2 ""))])]
  "! TARGET_SOFT_FLOAT"
  "
{
  rtx result;
  rtx target;

  if (! TARGET_29050)
    {
      target = operand_subword_force (operands[0], 0, SFmode);
      result = expand_binop (SImode, xor_optab,
			     operand_subword_force (operands[1], 0, SFmode),
			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
      if (result == 0)
	abort ();

      if (result != target)
	emit_move_insn (result, target);

      /* Make a place for REG_EQUAL.  */
      emit_move_insn (operands[0], operands[0]);
      DONE;
    }
}")

(define_expand "negdf2"
  [(parallel [(set (match_operand:DF 0 "register_operand" "")
		   (neg:DF (match_operand:DF 1 "register_operand" "")))
	      (clobber (match_scratch:SI 2 ""))])]
  "! TARGET_SOFT_FLOAT"
  "
{
  rtx result;
  rtx target;
  rtx insns;

  if (! TARGET_29050)
    {
      start_sequence ();
      target = operand_subword (operands[0], 0, 1, DFmode);
      result = expand_binop (SImode, xor_optab,
			     operand_subword_force (operands[1], 0, DFmode),
			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
      if (result == 0)
	abort ();

      if (result != target)
	emit_move_insn (result, target);
  
      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
		      operand_subword_force (operands[1], 1, DFmode));

      insns = get_insns ();
      end_sequence ();

      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
      DONE;
    }
}")

;; Sign extend and truncation operations.
(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
  ""
  "and %0,%1,255")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
  ""
  "and %0,%1,255")

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
  ""
  "consth %0,0")

(define_expand "extendqihi2"
  [(set (match_dup 2)
	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
		   (const_int 24)))
   (set (match_operand:HI 0 "gpc_reg_operand" "")
	(ashiftrt:SI (match_dup 2)
		     (const_int 24)))]
  ""
  "
{ operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = gen_reg_rtx (SImode); }")

(define_expand "extendqisi2"
  [(set (match_dup 2)
	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
		   (const_int 24)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(ashiftrt:SI (match_dup 2)
		     (const_int 24)))]
  ""
  "
{ operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = gen_reg_rtx (SImode); }")

(define_expand "extendhisi2"
  [(set (match_dup 2)
	(ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
		   (const_int 16)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(ashiftrt:SI (match_dup 2)
		     (const_int 16)))]
  ""
  "
{ operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = gen_reg_rtx (SImode); }")

;; Define the methods used to move data around.
;;
;; movsi:
;;
;; If storing into memory, force source into register.
(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
    operands[1] = copy_to_mode_reg (SImode, operands[1]);
  else if (spec_reg_operand (operands[0], SImode)
	   && ! (register_operand (operands[1], SImode)
		 || cint_16_operand (operands[1], SImode)))
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_expand "movpsi"
  [(set (match_operand:PSI 0 "general_operand" "")
	(match_operand:PSI 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! gpc_reg_operand (operands[1], PSImode))
    operands[1] = copy_to_mode_reg (PSImode, operands[1]);
  else if (spec_reg_operand (operands[0], PSImode)
	   && ! (register_operand (operands[1], PSImode)
		 || cint_16_operand (operands[1], PSImode)))
    operands[1] = force_reg (PSImode, operands[1]);
}")

(define_split
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(match_operand:SI 1 "long_const_operand" ""))]
  ""
  [(set (match_dup 0)
	(and:SI (match_dup 1)
		(const_int 65535)))
   (set (match_dup 0)
	(ior:SI (zero_extend:SI (match_dup 2))
		(and:SI (match_dup 1)
			(const_int -65536))))]
  " operands[2] = gen_lowpart (HImode, operands[0]); ")

;; Subroutines to load/store halfwords.  Operands 0 and 1 are the output and
;; input, respectively, except that the address is passed for a MEM instead 
;; of the MEM itself and the short item is passed in QImode.
;;
;; Operand 2 is a scratch general register and operand 3 is a scratch register
;; used for BP.  When called before reload, pseudos are passed for both
;; operands.  During reload, R_TAV is used for the general register, and
;; a reload register of class BR_REGS (R_VP) for BP.
;;
;; We have two versions of the store operations, for when halfword writes are
;; supported and when they are not.