a29k.md

gcc编译工具没有什么特别

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,a")
	(mult:SF (match_operand:SF 1 "register_operand" "%r,r")
		 (match_operand:SF 2 "register_operand" "r,r")))]
  "TARGET_29050"
  "@
   fmul %0,%1,%2
   fmac 4,%0,%1,%2"
  [(set_attr "type" "fmul,fam")])

;; FSUB
(define_expand "subsf3"
  [(set (match_operand:SF 0 "register_operand" "")
	(minus:SF (match_operand:SF 1 "register_operand" "")
		  (match_operand:SF 2 "register_operand" "")))]
  "! TARGET_SOFT_FLOAT"
  "")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(minus:SF (match_operand:SF 1 "register_operand" "r")
		  (match_operand:SF 2 "register_operand" "r")))]
  "! TARGET_29050"
  "fsub %0,%1,%2"
  [(set_attr "type" "fadd")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,a,a")
	(minus:SF (match_operand:SF 1 "register_operand" "r,0,r")
		  (match_operand:SF 2 "register_operand" "r,r,0")))]
  "TARGET_29050"
  "@
   fsub %0,%1,%2
   fmac 9,%0,%2,%2
   fmac 10,%0,%1,%1"
  [(set_attr "type" "fadd,fam,fam")])

;; INBYTE
(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
			 (const_int 8)
			 (ashift:PSI
			  (match_operand:PSI 2 "register_operand" "b")
			  (const_int 3)))
	(match_operand:SI 1 "srcb_operand" "rI"))]
  ""
  "inbyte %0,%0,%1")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (and:SI
		 (not:SI
		  (ashift:SI (const_int 255)
			     (ashift:PSI
			      (match_operand:PSI 3 "register_operand" "b")
			      (const_int 3))))
		 (match_operand:SI 1 "gpc_reg_operand" "r"))
		(ashift:SI (zero_extend:SI
			    (match_operand:QI 2 "srcb_operand" "rI"))
			   (ashift:PSI (match_dup 3) (const_int 3)))))]
  ""
  "inbyte %0,%1,%2")

;; INHW
(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
			 (const_int 16)
			 (ashift:PSI
			  (match_operand:PSI 2 "register_operand" "b")
			  (const_int 3)))
	(match_operand:SI 1 "srcb_operand" "rI"))]
  ""
  "inhw %0,%0,%1")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (and:SI
		 (not:SI
		  (ashift:SI (const_int 65535)
			     (ashift:PSI
			      (match_operand:PSI 3 "register_operand" "b")
			      (const_int 3))))
		 (match_operand:SI 1 "gpc_reg_operand" "r"))
		(ashift:SI (zero_extend:SI
			    (match_operand:HI 2 "srcb_operand" "rI"))
			   (ashift:PSI (match_dup 3) (const_int 3)))))]
  ""
  "inhw %0,%1,%2")

(define_expand "insv"
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
			 (match_operand:SI 1 "general_operand" "")
			 (match_operand:SI 2 "general_operand" ""))
	(match_operand:SI 3 "srcb_operand" ""))]
  ""
  "
{
  int size, pos;

  if (GET_CODE (operands[1]) != CONST_INT
      || GET_CODE (operands[2]) != CONST_INT)
    FAIL;

  size = INTVAL (operands[1]);
  pos = INTVAL (operands[2]);
  if ((size != 8 && size != 16) || pos % size != 0)
    FAIL;

  operands[2] = gen_rtx (ASHIFT, PSImode,
			 force_reg (PSImode, GEN_INT (pos / 8)),
			 GEN_INT (3));
}")

;; LOAD (also used by move insn).
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
			(const_int -4))))
   (set (match_operand:PSI 2 "register_operand" "=b")
	(truncate:PSI (match_dup 1)))]
  "! TARGET_DW_ENABLE"
  "load 0,16,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
  "TARGET_DW_ENABLE"
  "load 0,1,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
  "TARGET_DW_ENABLE"
  "load 0,1,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
  "TARGET_DW_ENABLE"
  "load 0,2,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
   (clobber (match_scratch:PSI 2 "=&b"))]
  "TARGET_DW_ENABLE"
  "load 0,17,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
   (clobber (match_scratch:PSI 2 "=&b"))]
  "TARGET_DW_ENABLE"
  "load 0,17,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
   (clobber (match_scratch:PSI 2 "=&b"))]
  "TARGET_DW_ENABLE"
  "load 0,18,%0,%1"
  [(set_attr "type" "load")])

;; LOADM
(define_expand "load_multiple"
  [(set (match_dup 4)
	(match_operand:PSI 2 "const_int_operand" ""))
   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
			  (match_operand:SI 1 "" ""))])]
  ""
  "
{
  int regno;
  int count;
  rtx from;
  int i;

  /* Support only loading a constant number of hard registers from memory.  */
  if (GET_CODE (operands[2]) != CONST_INT
      || operands[2] == const1_rtx
      || GET_CODE (operands[1]) != MEM
      || GET_CODE (operands[0]) != REG
      || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
    FAIL;

  count = INTVAL (operands[2]);
  regno = REGNO (operands[0]);

  /* CR gets set to the number of registers minus one.  */
  operands[2] = GEN_INT(count - 1);

  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
  from = memory_address (SImode, XEXP (operands[1], 0));
  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
					 gen_rtx (REG, SImode, regno),
					 gen_rtx (MEM, SImode, from));
  operands[4] = gen_reg_rtx (PSImode);

  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);

  for (i = 1; i < count; i++)
    XVECEXP (operands[3], 0, i + 2)
      = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
}")

;; Indicate that CR is used and is then clobbered.
(define_insn ""
  [(set (match_operand 0 "gpc_reg_operand" "=r")
	(match_operand 1 "memory_operand" "m"))
   (use (match_operand:PSI 2 "register_operand" "+c"))
   (clobber (match_dup 2))]
  "GET_MODE (operands[0]) == GET_MODE (operands[1])
   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
  "loadm 0,0,%0,%1"
  [(set_attr "type" "load")])

(define_insn ""
  [(match_parallel 0 "load_multiple_operation"
		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
			 (match_operand:SI 2 "memory_operand" "m"))
		    (use (match_operand:PSI 3 "register_operand" "+c"))
		    (clobber (match_dup 3))])]
  ""
  "loadm 0,0,%1,%2"
  [(set_attr "type" "load")])

;; MTSR (used also by move insn)
(define_insn ""
  [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
	(and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
		(match_operand:SI 2 "const_int_operand" "n,n")))]
  "masks_bits_for_special (operands[0], operands[2])"
  "@
   mtsr %0,%1
   mtsrim %0,%1")

(define_insn ""
  [(set (match_operand:PSI 0 "register_operand" "=h,h")
	(truncate:PSI
	 (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))]
  ""
  "@
   mtsr %0,%1
   mtsrim %0,%1")

;; MULTIPLY, MULTM, MULTMU
(define_insn "mulsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
		 (match_operand:SI 2 "gpc_reg_operand" "r")))
   (clobber (match_scratch:SI 3 "=&q"))]
  ""
  "multiply %0,%1,%2")

(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
   (clobber (match_scratch:SI 3 "=&q"))]
  "TARGET_MULTM"
  "multiply %L0,%1,%2\;multm %0,%1,%2"
  [(set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
   (clobber (reg:SI 180))]
  "reload_completed"
  [(parallel [(set (match_dup 3)
		   (mult:SI (match_dup 1) (match_dup 2)))
	      (clobber (reg:SI 180))])
   (parallel [(set (match_dup 4)
		   (truncate:SI
		    (lshiftrt:DI
		     (mult:DI (sign_extend:DI (match_dup 1))
			      (sign_extend:DI (match_dup 2)))
		     (const_int 32))))
	      (clobber (reg:SI 180))])]
  "
{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
			    
(define_insn "umulsidi3"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
   (clobber (match_scratch:SI 3 "=&q"))]
  "TARGET_MULTM"
  "multiplu %L0,%1,%2\;multmu %0,%1,%2"
  [(set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
   (clobber (reg:SI 180))]
  "reload_completed"
  [(parallel [(set (match_dup 3)
		   (mult:SI (match_dup 1) (match_dup 2)))
	      (clobber (reg:SI 180))])
   (parallel [(set (match_dup 4)
		   (truncate:SI
		    (lshiftrt:DI
		     (mult:DI (zero_extend:DI (match_dup 1))
			      (zero_extend:DI (match_dup 2)))
		     (const_int 32))))
	      (clobber (reg:SI 180))])]
  "
{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
			    
(define_insn "smulsi3_highpart"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(truncate:SI
	 (lshiftrt:DI
	  (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
		   (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
	  (const_int 32))))
   (clobber (match_scratch:SI 3 "=&q"))]
  "TARGET_MULTM"
  "multm %0,%1,%2")

(define_insn "umulsi3_highpart"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(truncate:SI
	 (lshiftrt:DI
	  (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
		   (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
	  (const_int 32))))
   (clobber (match_scratch:SI 3 "=&q"))]
  "TARGET_MULTM"
  "multmu %0,%1,%2")

;; NAND
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
  ""
  "nand %0,%1,%2")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
		(match_operand:SI 2 "const_int_operand" "K")))]
  ; Match TARGET_29050 in "orn" pattern for slightly better reload.
  "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
  "nand %0,%1,%C2")

;; NOR
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
  ""
  "nor %0,%1,%2")

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  ""
  "nor %0,%1,0")

;; OR/ORN
(define_expand "iorsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
		(match_operand:SI 2 "srcb_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
		(match_operand:SI 2 "srcb_operand" "rI")))]
  "! TARGET_29050"
  "or %0,%1,%2")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
		(match_operand:SI 2 "and_operand" "rI,K")))]
  "TARGET_29050"
  "@
   or %0,%1,%2
   orn %0,%1,%C2")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
  "TARGET_29050"
  "@
   orn %0,%2,%1
   nand %0,%1,%C2")


;; SLL (also used by move insn)
(define_insn "nop"
  [(const_int 0)]
  ""
  "aseq 0x40,gr1,gr1")

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		   (match_operand:QI 2 "srcb_operand" "rn")))]
  ""
  "sll %0,%1,%Q2")

;; SQRT
(define_insn "sqrtsf2"
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
  "TARGET_29050"
  "sqrt %0,%1,1"
  [(set_attr "type" "fsqrt")])

(define_insn "sqrtdf2"
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")