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   (use (match_operand:SI 4 "register_operand" "3"))]
  ""
  "divide %0,%1,%2")

;; DIVIDU
;;
;; Similar to DIVIDE.
(define_expand "udivmodsi4"
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
			    (match_operand:SI 2 "gpc_reg_operand" "")))
	      (set (match_operand:SI 3 "gpc_reg_operand" "")
		   (umod:SI (match_dup 1)
			    (match_dup 2)))
	      (use (const_int 0))])]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		 (match_operand:SI 2 "gpc_reg_operand" "r")))
   (set (match_operand:SI 3 "register_operand" "=q")
	(umod:SI (match_dup 1)
		 (match_dup 2)))
   (use (match_operand:SI 4 "const_int_operand" "3"))]
  ""
  "dividu %0,%1,%2")

;; DMAC/DMSM
(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a,*r")
	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A")
			  (match_operand:DF 2 "register_operand" "r,r"))
		 (match_operand:DF 3 "register_operand" "0,*r")))]
  "TARGET_29050"
  "@
   dmac 0,%0,%1,%2
   dmsm %0,%2,%3"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
			  (match_operand:DF 2 "register_operand" "r"))
		 (match_operand:DF 3 "register_operand" "0")))]
  "TARGET_29050"
  "dmac 1,%0,%2,%1"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r")
			   (match_operand:DF 2 "register_operand" "r"))
		  (match_operand:DF 3 "register_operand" "0")))]
  "TARGET_29050"
  "dmac 2,%0,%1,%2"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r")
			   (neg:DF (match_operand:DF 2 "register_operand" "r")))
		  (match_operand:DF 3 "register_operand" "0")))]
  "TARGET_29050"
  "dmac 3,%0,%1,%2"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
		 (match_operand:DF 2 "register_operand" "r")))]
  "TARGET_29050"
  "dmac 5,%0,%2,%1"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
		  (match_operand:DF 2 "register_operand" "0")))]
  "TARGET_29050"
  "dmac 11,%0,%1,%1"
  [(set_attr "type" "dam")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=a")
	(neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
			 (match_operand:DF 2 "register_operand" "0"))))]
  "TARGET_29050"
  "dmac 11,%0,%1,%1"
  [(set_attr "type" "dam")])

(define_insn ""
 [(set (match_operand:DF 0 "register_operand" "=r,r,a")
       (neg:DF (match_operand:DF 1 "register_operand" "0,r,r")))
  (clobber (match_scratch:SI 2 "=&r,&r,X"))]
 "TARGET_29050"
 "@
  cpeq %2,gr1,gr1\;xor %0,%1,%2
  cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
  dmac 13,%0,%1,%1"
 [(set_attr "type" "multi,multi,dam")])

;; DMUL
(define_expand "muldf3"
  [(set (match_operand:DF 0 "register_operand" "")
	(mult:DF (match_operand:DF 1 "register_operand" "")
		 (match_operand:DF 2 "register_operand" "")))]
  "! TARGET_SOFT_FLOAT"
  "")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(mult:DF (match_operand:DF 1 "register_operand" "%r")
		 (match_operand:DF 2 "register_operand" "r")))]
  "! TARGET_29050"
  "dmul %0,%1,%2"
  [(set_attr "type" "dmul")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,a")
	(mult:DF (match_operand:DF 1 "register_operand" "%r,r")
		 (match_operand:DF 2 "register_operand" "r,r")))]
  "TARGET_29050"
  "@
   dmul %0,%1,%2
   dmac 4,%0,%1,%2"
  [(set_attr "type" "dmul,dam")])

;; DSUB
(define_expand "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(minus:DF (match_operand:DF 1 "register_operand" "r")
		  (match_operand:DF 2 "register_operand" "r")))]
  "! TARGET_SOFT_FLOAT"
  "")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(minus:DF (match_operand:DF 1 "register_operand" "r")
		  (match_operand:DF 2 "register_operand" "r")))]
  "! TARGET_29050"
  "dsub %0,%1,%2"
  [(set_attr "type" "fadd")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,a,a")
	(minus:DF (match_operand:DF 1 "register_operand" "r,0,r")
		  (match_operand:DF 2 "register_operand" "r,r,0")))]
  "TARGET_29050"
  "@
   dsub %0,%1,%2
   dmac 9,%0,%2,%2
   dmac 10,%0,%1,%1"
  [(set_attr "type" "fadd,dam,dam")])

;; EXBYTE
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
			(const_int -256))
		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
				 (const_int 8)
				 (ashift:PSI
				  (match_operand:PSI 3 "register_operand" "b")
				  (const_int 3)))))]
  ""
  "exbyte %0,%2,%1")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
			 (const_int 8)
			 (ashift:PSI
			  (match_operand:PSI 2 "register_operand" "b")
			  (const_int 3))))]
  ""
  "exbyte %0,%1,0")

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
			 (const_int 8)
			 (match_operand:PSI 1 "const_24_operand" ""))
	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
			 (const_int 8)
			 (ashift:PSI
			  (match_operand:PSI 3 "register_operand" "b")
			  (const_int 3))))]
  ""
  "exbyte %0,%2,%0")

(define_expand "extzv"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
			 (match_operand:SI 2 "general_operand" "")
			 (match_operand:SI 3 "general_operand" "")))]
  ""
  "
{
  int size, pos;

  if (GET_CODE (operands[2]) != CONST_INT
      || GET_CODE (operands[3]) != CONST_INT)
    FAIL;

  size = INTVAL (operands[2]);
  pos = INTVAL (operands[3]);

  /* Can't do this unless a byte extraction.  If extracting the high
     or low byte, don't do this because a shift or AND is shorter.
     Don't do 16-bit extracts, since the only two are the high and low
     ends, and it is faster to do them with CONSTH and SRL.  */

  if (size != 8 || (pos != 8 && pos != 16))
    FAIL;

  operands[3] = gen_rtx (ASHIFT, PSImode,
			 force_reg (PSImode, GEN_INT (pos / 8)),
			 GEN_INT (3));

}")

;; EXHW
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
		(const_int -65536))
		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
				 (const_int 16)
				 (ashift:PSI
				  (match_operand:PSI 3 "register_operand" "b")
				  (const_int 3)))))]
  ""
  "exhw %0,%2,%1")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
			 (const_int 16)
			 (ashift:PSI
			  (match_operand:PSI 2 "register_operand" "b")
			  (const_int 3))))]
  ""
  "exhw %0,%1,0")

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
			 (const_int 16)
			 (match_operand:PSI 1 "const_16_operand" ""))
	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
			 (const_int 16)
			 (ashift:PSI
			  (match_operand:PSI 3 "register_operand" "b")
			  (const_int 3))))]
  ""
  "exhw %0,%2,%0")

;; EXHWS
;;
;; This is probably unused.  The high-order 16-bits are obtained with an SRA
;; insn.  The low-order 16 bits are a sign-extend, which is a pair of
;; shifts.  Setting BP followed by the insn is equivalent, so we don't
;; bother going to any trouble to generate this insn.

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
			 (const_int 16)
			 (ashift:PSI
			  (match_operand:PSI 2 "register_operand" "b")
			  (const_int 3))))]
  ""
  "exhws %0,%1")

;; EXTRACT
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		   (match_operand:PSI 2 "register_operand" "f")))]
  ""
  "extract %0,%1,%1")

(define_expand "rotlsi3"
  [(set (match_dup 3)
	(match_operand:SI 2 "gpc_reg_or_immediate_operand" ""))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
		   (match_dup 3)))]
  ""
  "
{ operands[2] = gen_lowpart (PSImode, operands[2]);
  operands[3] = gen_reg_rtx (PSImode);
}")

;; It would be nice to be able to have a define_split corresponding to the
;; above, but there is no way to tell combine we need a PSImode temporary.
;; If we put a (clobber (scratch:PSI)) there, combine would merge the above
;; two insns.  This is bad because it then thinks only one insn is needed.

;; FADD
(define_expand "addsf3"
  [(set (match_operand:SF 0 "register_operand" "")
	(plus:SF (match_operand:SF 1 "register_operand" "")
		 (match_operand:SF 2 "register_operand" "")))]
  "! TARGET_SOFT_FLOAT"
  "")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(plus:SF (match_operand:SF 1 "register_operand" "%r")
		 (match_operand:SF 2 "register_operand" "r")))]
  "! TARGET_29050"
  "fadd %0,%1,%2"
  [(set_attr "type" "fadd")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,a")
	(plus:SF (match_operand:SF 1 "register_operand" "%r,r")
		 (match_operand:SF 2 "register_operand" "r,0")))]
  "TARGET_29050"
  "@
   fadd %0,%1,%2
   fmac 8,%0,%1,%1"
  [(set_attr "type" "fadd,fam")])

;; FDIV
(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(div:SF (match_operand:SF 1 "register_operand" "=r")
		(match_operand:SF 2 "register_operand" "r")))]
  "! TARGET_SOFT_FLOAT"
  "fdiv %0,%1,%2"
  [(set_attr "type" "fdiv")])

;; FDMUL
(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
		 (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
  "! TARGET_SOFT_FLOAT"
  "fdmul %0,%1,%2")

;; FMAC/FMSM
(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a,*r")
	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A")
			  (match_operand:SF 2 "register_operand" "r,r"))
		 (match_operand:SF 3 "register_operand" "0,*r")))]
  "TARGET_29050"
  "@
   fmac 0,%0,%1,%2
   fmsm %0,%2,%3"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
			  (match_operand:SF 2 "register_operand" "r"))
		 (match_operand:SF 3 "register_operand" "0")))]
  "TARGET_29050"
  "fmac 1,%0,%2,%1"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
			   (match_operand:SF 2 "register_operand" "r"))
		  (match_operand:SF 3 "register_operand" "0")))]
  "TARGET_29050"
  "fmac 2,%0,%1,%2"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
			   (match_operand:SF 2 "register_operand" "r"))
		  (match_operand:SF 3 "register_operand" "0")))]
  "TARGET_29050"
  "fmac 3,%0,%2,%1"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
		 (match_operand:SF 2 "register_operand" "r")))]
  "TARGET_29050"
  "fmac 5,%0,%2,%1"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
		  (match_operand:SF 2 "register_operand" "0")))]
  "TARGET_29050"
  "fmac 11,%0,%1,%1"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=a")
	(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
			 (match_operand:SF 2 "register_operand" "0"))))]
  "TARGET_29050"
  "fmac 11,%0,%1,%1"
  [(set_attr "type" "fam")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,a")
	(neg:SF (match_operand:SF 1 "register_operand" "r,r")))
   (clobber (match_scratch:SI 2 "=&r,X"))]
  "TARGET_29050"
  "@
   cpeq %2,gr1,gr1\;xor %0,%1,%2
   fmac 13,%0,%1,%1"
  [(set_attr "type" "multi,fam")])

;; FMUL
(define_expand "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "")
	(mult:SF (match_operand:SF 1 "register_operand" "")
		 (match_operand:SF 2 "register_operand" "")))]
  "! TARGET_SOFT_FLOAT"
  "")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(mult:SF (match_operand:SF 1 "register_operand" "%r")
		 (match_operand:SF 2 "register_operand" "r")))]
  "! TARGET_29050"
  "fmul %0,%1,%2"
  [(set_attr "type" "fmul")])