📄 a29k.h
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Aside from that, you can include as many other registers as you like. */#define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }/* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. We allocate in the following order: gr116-gr120 (not used for anything but temps) gr96-gr111 (function return values, reverse order) argument registers (160-175) lr0-lr127 (locals, saved) acc3-0 (acc0 special) everything else */#define REG_ALLOC_ORDER \ {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120), \ R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107), \ R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102), \ R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96), \ R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5), \ R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11), \ R_AR (12), R_AR (13), R_AR (14), R_AR (15), \ R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5), \ R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11), \ R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17), \ R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23), \ R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29), \ R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35), \ R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41), \ R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), \ R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53), \ R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59), \ R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65), \ R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71), \ R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77), \ R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83), \ R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89), \ R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95), \ R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101), \ R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106), \ R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111), \ R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116), \ R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \ R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \ R_LR (127), \ R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0), \ R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \ R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \ R_GR (127), \ R_FP, R_BP, R_FC, R_CR, R_Q, \ R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC, \ R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS, \ R_EXO, \ R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), \ R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11), \ R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17), \ R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23), \ R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29), \ R_KR (30), R_KR (31) }/* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */#define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On 29k, the cpu registers can hold any mode. But a double-precision floating-point value should start at an even register. The special registers cannot hold floating-point values, BP, CR, and FC cannot hold integer or floating-point values, and the accumulators cannot hold integer values. DImode and larger values should start at an even register just like DFmode values, even though the instruction set doesn't require it, in order to prevent reload from aborting due to a modes_equiv_for_class_p failure. (I'd like to use the "?:" syntax to make this more readable, but Sun's compiler doesn't seem to accept it.) */#define HARD_REGNO_MODE_OK(REGNO, MODE) \(((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3) \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \ || ((REGNO) >= R_BP && (REGNO) <= R_CR \ && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT) \ || ((REGNO) >= R_Q && (REGNO) < R_ACU (0) \ && GET_MODE_CLASS (MODE) != MODE_FLOAT \ && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \ || (((REGNO) < R_BP || (REGNO) >= R_KR (0)) \ && ((((REGNO) & 1) == 0) \ || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))/* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. On the 29k, normally we'd just have problems with DFmode because of the even alignment. However, we also have to be a bit concerned about the special register's restriction to non-floating and the floating-point accumulator's restriction to only floating. This probably won't cause any great inefficiencies in practice. */#define MODES_TIEABLE_P(MODE1, MODE2) \ ((MODE1) == (MODE2) \ || (GET_MODE_CLASS (MODE1) == MODE_INT \ && GET_MODE_CLASS (MODE2) == MODE_INT))/* Specify the registers used for certain standard purposes. The values of these macros are register numbers. *//* 29k pc isn't overloaded on a register that the compiler knows about. *//* #define PC_REGNUM *//* Register to use for pushing function arguments. */#define STACK_POINTER_REGNUM R_GR (125)/* Base register for access to local variables of the function. */#define FRAME_POINTER_REGNUM R_FP/* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */#define FRAME_POINTER_REQUIRED 0/* Base register for access to arguments of the function. */#define ARG_POINTER_REGNUM R_FP/* Register in which static-chain is passed to a function. */#define STATIC_CHAIN_REGNUM R_SLP/* Register in which address to store a structure value is passed to a function. */#define STRUCT_VALUE_REGNUM R_LRP /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS, BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS. LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single register. The latter two classes are used to represent the floating-point accumulator registers in the 29050. We also define the union class FLOAT_REGS to represent any register that can be used to hold a floating-point value. The union of SPECIAL_REGS and ACCUM_REGS isn't useful as the former cannot contain floating-point and the latter can only contain floating-point. */enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS, Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES };#define N_REG_CLASSES (int) LIM_REG_CLASSES/* Give names of register classes as strings for dump file. */#define REG_CLASS_NAMES \ {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \ "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS", \ "ALL_REGS" }/* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */#define REG_CLASS_CONTENTS \ { {0, 0, 0, 0, 0, 0, 0, 0}, \ {0, 1, 0, 0, 0, 0, 0, 0}, \ {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff}, \ {0, 0, 0, 0, 0, 0x20000, 0, 0}, \ {0, 0, 0, 0, 0, 0x40000, 0, 0}, \ {0, 0, 0, 0, 0, 0x80000, 0, 0}, \ {0, 0, 0, 0, 0, 0x100000, 0, 0}, \ {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0}, \ {0, 0, 0, 0, 0, 0, 0x100, 0}, \ {0, 0, 0, 0, 0, 0, 0xf00, 0}, \ {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, \ {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} }/* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */#define REGNO_REG_CLASS(REGNO) \ ((REGNO) == R_BP ? BP_REGS \ : (REGNO) == R_FC ? FC_REGS \ : (REGNO) == R_CR ? CR_REGS \ : (REGNO) == R_Q ? Q_REGS \ : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \ : (REGNO) == R_ACU (0) ? ACCUM0_REGS \ : (REGNO) >= R_KR (0) ? GENERAL_REGS \ : (REGNO) > R_ACU (0) ? ACCUM_REGS \ : (REGNO) == R_LR (0) ? LR0_REGS \ : GENERAL_REGS)/* The class value for index registers, and the one for base regs. */#define INDEX_REG_CLASS NO_REGS#define BASE_REG_CLASS GENERAL_REGS/* Get reg_class from a letter such as appears in the machine description. */#define REG_CLASS_FROM_LETTER(C) \ ((C) == 'r' ? GENERAL_REGS \ : (C) == 'l' ? LR0_REGS \ : (C) == 'b' ? BP_REGS \ : (C) == 'f' ? FC_REGS \ : (C) == 'c' ? CR_REGS \ : (C) == 'q' ? Q_REGS \ : (C) == 'h' ? SPECIAL_REGS \ : (C) == 'a' ? ACCUM_REGS \ : (C) == 'A' ? ACCUM0_REGS \ : (C) == 'f' ? FLOAT_REGS \ : NO_REGS)/* Define this macro to change register usage conditional on target flags. On the 29k, we use this to change the register names for kernel mapping. */#define CONDITIONAL_REGISTER_USAGE \ { \ char *p; \ int i; \ \ if (TARGET_KERNEL_REGISTERS) \ for (i = 0; i < 32; i++) \ { \ p = reg_names[i]; \ reg_names[i] = reg_names[R_KR (i)]; \ reg_names[R_KR (i)] = p; \ } \ }/* The letters I, J, K, L, M, N, O, and P in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For 29k: `I' is used for the range of constants most insns can contain. `J' is for the few 16-bit insns. `K' is a constant whose high-order 24 bits are all one `L' is a HImode constant whose high-order 8 bits are all one `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN) `N' is a 32-bit constant whose negative is 8 bits `O' is the 32-bit constant 0x80000000, any constant with low-order 16 bits zero for 29050. `P' is a HImode constant whose negative is 8 bits */#define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (unsigned) (VALUE) < 0x100 \ : (C) == 'J' ? (unsigned) (VALUE) < 0x10000 \ : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00 \ : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00 \ : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000 \ : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256) \ : (C) == 'O' ? ((VALUE) == 0x80000000 \ || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \ : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0 \ && ((VALUE) | 0xffff0000) > -256) \ : 0)/* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. All floating-point constants are valid on 29k. */#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1/* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS/* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ secondary_reload_class (CLASS, MODE, IN)/* This function is used to get the address of an object. */extern struct rtx_def *a29k_get_reloaded_address ();/* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. On 29k, this is the size of MODE in words except that the floating-point accumulators only require one word for anything they can hold. */#define CLASS_MAX_NREGS(CLASS, MODE) \ (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)/* Define the cost of moving between registers of various classes. Everything⌨️ 快捷键说明
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