i386.md

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	(match_operand:SI 1 "nonmemory_operand" "rn"))]
  "flag_pic"
  "* return AS1 (push%L0,%1);"
  [(set_attr "memory" "store")])

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<")
	(match_operand:SI 1 "nonmemory_operand" "ri"))]
  "!flag_pic"
  "* return AS1 (push%L0,%1);"
  [(set_attr "memory" "store")])

;; On a 386, it is faster to push MEM directly.

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<")
	(match_operand:SI 1 "memory_operand" "m"))]
  "TARGET_PUSH_MEMORY"
  "* return AS1 (push%L0,%1);"
  [(set_attr "type" "memory")
   (set_attr "memory" "load")])

;; General case of fullword move.

;; If generating PIC code and operands[1] is a symbolic CONST, emit a
;; move to get the address of the symbolic object from the GOT.

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  extern int flag_pic;

  if (flag_pic && SYMBOLIC_CONST (operands[1]))
    emit_pic_move (operands, SImode);

  /* Don't generate memory->memory moves, go through a register */
  else if (TARGET_MOVE
	   && no_new_pseudos == 0
	   && GET_CODE (operands[0]) == MEM
	   && GET_CODE (operands[1]) == MEM)
    {
      operands[1] = force_reg (SImode, operands[1]);
    }
}")

;; On i486, incl reg is faster than movl $1,reg.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g,r,r")
	(match_operand:SI 1 "general_operand" "rn,i,m"))]
  "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
    || (GET_CODE (operands[1]) != MEM))
   && flag_pic"
  "*
{
  rtx link;

  /* K6: mov reg,0 is slightly faster than xor reg,reg but is 3 bytes
     longer.  */
  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
      && operands[1] == const0_rtx && REG_P (operands[0]))
    return AS2 (xor%L0,%0,%0);

  if (operands[1] == const1_rtx
      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    /* Fastest way to change a 0 to a 1.  */
    return AS1 (inc%L0,%0);

  if (SYMBOLIC_CONST (operands[1]))
    return AS2 (lea%L0,%a1,%0);

  return AS2 (mov%L0,%1,%0);
}"
  [(set_attr "type" "integer,integer,memory")
   (set_attr "memory" "*,*,load")])

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g,r")
	(match_operand:SI 1 "general_operand" "ri,m"))]
  "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
    || (GET_CODE (operands[1]) != MEM))
   && !flag_pic"
  "*
{
  rtx link;

  /* Use of xor was disabled for AMD K6 as recommended by the Optimization
     Manual.  My test shows, that this generally hurts the performance, because
     mov is longer and takes longer to decode and decoding is the main
     bottleneck of K6 when executing GCC code.  */

  if (operands[1] == const0_rtx && REG_P (operands[0]))
    return AS2 (xor%L0,%0,%0);

  if (operands[1] == const1_rtx
      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    /* Fastest way to change a 0 to a 1.  */
    return AS1 (inc%L0,%0);

  return AS2 (mov%L0,%1,%0);
}"
  [(set_attr "type" "integer,memory")
   (set_attr "memory" "*,load")])

(define_insn ""
  [(set (match_operand:HI 0 "push_operand" "=<")
	(match_operand:HI 1 "nonmemory_operand" "ri"))]
  ""
  "* return AS1 (push%W0,%1);"
  [(set_attr "type" "memory")
   (set_attr "memory" "store")])

(define_insn ""
  [(set (match_operand:HI 0 "push_operand" "=<")
	(match_operand:HI 1 "memory_operand" "m"))]
  "TARGET_PUSH_MEMORY"
  "* return AS1 (push%W0,%1);"
  [(set_attr "type" "memory")
   (set_attr "memory" "load")])

;; On i486, an incl and movl are both faster than incw and movw.

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  /* Don't generate memory->memory moves, go through a register */
  if (TARGET_MOVE
      && no_new_pseudos == 0
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)
    {
      operands[1] = force_reg (HImode, operands[1]);
    }
}")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=g,r")
	(match_operand:HI 1 "general_operand" "ri,m"))]
  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
  "*
{
  rtx link;
  if (REG_P (operands[0]) && operands[1] == const0_rtx)
    return AS2 (xor%L0,%k0,%k0);

  if (REG_P (operands[0]) && operands[1] == const1_rtx 
      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    /* Fastest way to change a 0 to a 1.  */
    return AS1 (inc%L0,%k0);

  if (REG_P (operands[0]))
    {
      if (i386_aligned_p (operands[1]))
	{
	  operands[1] = i386_sext16_if_const (operands[1]);
	  return AS2 (mov%L0,%k1,%k0);
	}
      if (! TARGET_ZERO_EXTEND_WITH_AND)
	{
	  /* movzwl is faster than movw on the Pentium Pro,
	   * although not as fast as an aligned movl. */
#ifdef INTEL_SYNTAX
	  return AS2 (movzx,%1,%k0);
#else
	  return AS2 (movz%W0%L0,%1,%k0);
#endif
	}
    }

  return AS2 (mov%W0,%1,%0);
}"
  [(set_attr "type" "integer,memory")
   (set_attr "memory" "*,load")])

(define_expand "movstricthi"
  [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  /* Don't generate memory->memory moves, go through a register */
  if (TARGET_MOVE
      && no_new_pseudos == 0
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)
    {
      operands[1] = force_reg (HImode, operands[1]);
    }
}")

(define_insn ""
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
	(match_operand:HI 1 "general_operand" "ri,m"))]
  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
  "*
{
  rtx link;

  /* Use of xor was disabled for AMD K6 as recommended by the Optimization
     Manual.  My test shows, that this generally hurts the performance, because
     mov is longer and takes longer to decode and decoding is the main
     bottleneck of K6 when executing GCC code.  */

  if (operands[1] == const0_rtx && REG_P (operands[0]))
    return AS2 (xor%W0,%0,%0);

  if (operands[1] == const1_rtx
      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    /* Fastest way to change a 0 to a 1.  */
    return AS1 (inc%W0,%0);

  return AS2 (mov%W0,%1,%0);
}"
  [(set_attr "type" "integer,memory")])

;; emit_push_insn when it calls move_by_pieces
;; requires an insn to "push a byte".
;; But actually we use pushw, which has the effect of rounding
;; the amount pushed up to a halfword.
(define_insn ""
  [(set (match_operand:QI 0 "push_operand" "=<")
	(match_operand:QI 1 "const_int_operand" "n"))]
  ""
  "* return AS1(push%W0,%1);")

(define_insn ""
  [(set (match_operand:QI 0 "push_operand" "=<")
	(match_operand:QI 1 "register_operand" "q"))]
  ""
  "*
{
  operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]));
  return AS1 (push%W0,%1);
}")

;; On i486, incb reg is faster than movb $1,reg.

;; ??? Do a recognizer for zero_extract that looks just like this, but reads
;; or writes %ah, %bh, %ch, %dh.

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  /* Don't generate memory->memory moves, go through a register */
  if (TARGET_MOVE
      && no_new_pseudos == 0
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)
    {
      operands[1] = force_reg (QImode, operands[1]);
    }
}")

(define_insn ""
  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,*r,qm")
	(match_operand:QI 1 "general_operand" "*g,*rn,qn"))]
  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
  "*
{
  rtx link;

  /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8.
     It is at least as fast as xor on any processor except a Pentium. */

  if (operands[1] == const1_rtx
      && TARGET_PENTIUM
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    {
      /* Fastest way to change a 0 to a 1.
	 If inc%B0 isn't allowed, use inc%L0.  */
      if (NON_QI_REG_P (operands[0]))
	return AS1 (inc%L0,%k0);
      else
	return AS1 (inc%B0,%0);
    }

  /* If mov%B0 isn't allowed for one of these regs, use mov%L0.  */
  if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
    return (AS2 (mov%L0,%k1,%k0));

  return (AS2 (mov%B0,%1,%0));
}")

;; If it becomes necessary to support movstrictqi into %esi or %edi,
;; use the insn sequence:
;;
;;	shrdl $8,srcreg,dstreg
;;	rorl $24,dstreg
;;
;; If operands[1] is a constant, then an andl/orl sequence would be
;; faster.

(define_expand "movstrictqi"
  [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  /* Don't generate memory->memory moves, go through a register */
  if (TARGET_MOVE
      && no_new_pseudos == 0
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)
    {
      operands[1] = force_reg (QImode, operands[1]);
    }
}")

(define_insn ""
  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
	(match_operand:QI 1 "general_operand" "*qn,m"))]
  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
  "*
{
  rtx link;

  /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8.  */

  if (operands[1] == const1_rtx
      && TARGET_PENTIUM
      && ! NON_QI_REG_P (operands[0])
      && (link = find_reg_note (insn, REG_WAS_0, 0))
      /* Make sure the insn that stored the 0 is still present.  */
      && ! INSN_DELETED_P (XEXP (link, 0))
      && GET_CODE (XEXP (link, 0)) != NOTE
      /* Make sure cross jumping didn't happen here.  */
      && no_labels_between_p (XEXP (link, 0), insn)
      /* Make sure the reg hasn't been clobbered.  */
      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
    /* Fastest way to change a 0 to a 1.  */
    return AS1 (inc%B0,%0);

  /* If mov%B0 isn't allowed for one of these regs, use mov%L0.  */
  if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
    {
      abort ();
      return (AS2 (mov%L0,%k1,%k0));
    }

  return AS2 (mov%B0,%1,%0);
}")

(define_insn "movsf_push"
  [(set (match_operand:SF 0 "push_operand" "=<,<")
	(match_operand:SF 1 "general_operand" "*rfF,m"))]
  "TARGET_PUSH_MEMORY || GET_CODE (operands[1]) != MEM 
   || reload_in_progress || reload_completed"
  "*
{
  if (STACK_REG_P (operands[1]))
    {
      rtx xops[3];

      if (! STACK_TOP_P (operands[1]))
        abort ();

      xops[0] = AT_SP (SFmode);
      xops[1] = GEN_INT (4);
      xops[2] = stack_pointer_rtx;

      output_asm_insn (AS2 (sub%L2,%1,%2), xops);

      if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
        output_asm_insn (AS1 (fstp%S0,%0), xops);
      else
        output_asm_insn (AS1 (fst%S0,%0), xops);

      RET;
    }

  return AS1 (push%L0,%1);
}")

(define_split
  [(set (match_operand:SF 0 "push_operand" "")
        (match_operand:SF 1 "general_operand" ""))]
  "reload_completed && STACK_REG_P (operands[1])"
  [(set (reg:SI 7)
        (minus:SI (reg:SI 7) (const_int 4)))
   (set (mem:SF (reg:SI 7))
        (match_dup 1))]
  "")

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "
{
  /* Don't generate memory->memory moves, go through a register */
  if (TARGET_MOVE
      && no_new_pseudos == 0
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)