i386.md

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  i386_compare_op1 = operands[1];
  DONE;
}")

(define_insn "cmphi_1"
  [(set (cc0)
	(compare (match_operand:HI 0 "nonimmediate_operand" "mr,r")
		 (match_operand:HI 1 "general_operand" "ri,mr")))]
  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
  "* return AS2 (cmp%W0,%1,%0);"
  [(set_attr "type" "compare")])

(define_expand "cmphi"
  [(set (cc0)
	(compare (match_operand:HI 0 "nonimmediate_operand" "")
		 (match_operand:HI 1 "general_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
    operands[0] = force_reg (HImode, operands[0]);

  i386_compare_gen = gen_cmphi_1;
  i386_compare_op0 = operands[0];
  i386_compare_op1 = operands[1];
  DONE;
}")

(define_insn "cmpqi_1"
  [(set (cc0)
	(compare (match_operand:QI 0 "nonimmediate_operand" "q,mq")
		 (match_operand:QI 1 "general_operand" "qm,nq")))]
  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
  "* return AS2 (cmp%B0,%1,%0);"
  [(set_attr "type" "compare")])

(define_expand "cmpqi"
  [(set (cc0)
	(compare (match_operand:QI 0 "nonimmediate_operand" "")
		 (match_operand:QI 1 "general_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
    operands[0] = force_reg (QImode, operands[0]);

  i386_compare_gen = gen_cmpqi_1;
  i386_compare_op0 = operands[0];
  i386_compare_op1 = operands[1];
  DONE;
}")

;; These implement float point compares.  For each of DFmode and
;; SFmode, there is the normal insn, and an insn where the second operand
;; is converted to the desired mode.

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:XF 0 "register_operand" "f")
			 (match_operand:XF 1 "register_operand" "f")]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:XF 0 "register_operand" "f")
			 (float_extend:XF
			  (match_operand:DF 1 "nonimmediate_operand" "fm"))]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(float_extend:XF
			  (match_operand:DF 0 "nonimmediate_operand" "fm"))
			 (match_operand:XF 1 "register_operand" "f")]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:XF 0 "register_operand" "f")
			 (float_extend:XF
			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(float_extend:XF
			  (match_operand:SF 0 "nonimmediate_operand" "fm"))
			 (match_operand:XF 1 "register_operand" "f")]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(compare:CCFPEQ (match_operand:XF 0 "register_operand" "f")
			(match_operand:XF 1 "register_operand" "f")))
   (clobber (match_scratch:HI 2 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:DF 0 "nonimmediate_operand" "f,fm")
			 (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
   (clobber (match_scratch:HI 3 "=a,a"))]
  "TARGET_80387
   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:DF 0 "register_operand" "f")
			 (float_extend:DF
			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(float_extend:DF
			  (match_operand:SF 0 "nonimmediate_operand" "fm"))
			 (match_operand:DF 1 "register_operand" "f")]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(float_extend:DF
			  (match_operand:SF 0 "register_operand" "f"))
			 (match_operand:DF 1 "nonimmediate_operand" "fm")]))
   (clobber (match_scratch:HI 3 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
			(match_operand:DF 1 "register_operand" "f")))
   (clobber (match_scratch:HI 2 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

;; These two insns will never be generated by combine due to the mode of
;; the COMPARE.
;(define_insn ""
;  [(set (cc0)
;	(compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
;			(float_extend:DF
;			 (match_operand:SF 1 "register_operand" "f"))))
;   (clobber (match_scratch:HI 2 "=a"))]
;  "TARGET_80387"
;  "* return output_float_compare (insn, operands);")
;
;(define_insn ""
;  [(set (cc0)
;	(compare:CCFPEQ (float_extend:DF
;			 (match_operand:SF 0 "register_operand" "f"))
;			(match_operand:DF 1 "register_operand" "f")))
;   (clobber (match_scratch:HI 2 "=a"))]
;  "TARGET_80387"
;  "* return output_float_compare (insn, operands);")

(define_insn "*cmpsf_cc_1"
  [(set (cc0)
	(match_operator 2 "VOIDmode_compare_op"
			[(match_operand:SF 0 "nonimmediate_operand" "f,fm")
			 (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
   (clobber (match_scratch:HI 3 "=a,a"))]
  "TARGET_80387
   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_insn ""
  [(set (cc0)
	(compare:CCFPEQ (match_operand:SF 0 "register_operand" "f")
			(match_operand:SF 1 "register_operand" "f")))
   (clobber (match_scratch:HI 2 "=a"))]
  "TARGET_80387"
  "* return output_float_compare (insn, operands);"
  [(set_attr "type" "fcompare")])

(define_expand "cmpxf"
  [(set (cc0)
	(compare (match_operand:XF 0 "register_operand" "")
		 (match_operand:XF 1 "register_operand" "")))]
  "TARGET_80387"
  "
{
  i386_compare_gen = gen_cmpxf_cc;
  i386_compare_gen_eq = gen_cmpxf_ccfpeq;
  i386_compare_op0 = operands[0];
  i386_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "")
		 (match_operand:DF 1 "general_operand" "")))]
  "TARGET_80387"
  "
{
  i386_compare_gen = gen_cmpdf_cc;
  i386_compare_gen_eq = gen_cmpdf_ccfpeq;
  i386_compare_op0 = operands[0];
  i386_compare_op1 = (immediate_operand (operands[1], DFmode))
			? copy_to_mode_reg (DFmode, operands[1]) : operands[1];
  DONE;
}")

(define_expand "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "register_operand" "")
		 (match_operand:SF 1 "general_operand" "")))]
  "TARGET_80387"
  "
{
  i386_compare_gen = gen_cmpsf_cc;
  i386_compare_gen_eq = gen_cmpsf_ccfpeq;
  i386_compare_op0 = operands[0];
  i386_compare_op1 = (immediate_operand (operands[1], SFmode))
			? copy_to_mode_reg (SFmode, operands[1]) : operands[1];
  DONE;
}")

(define_expand "cmpxf_cc"
  [(parallel [(set (cc0)
		   (compare (match_operand:XF 0 "register_operand" "")
			    (match_operand:XF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "")

(define_expand "cmpxf_ccfpeq"
  [(parallel [(set (cc0)
		   (compare:CCFPEQ (match_operand:XF 0 "register_operand" "")
				   (match_operand:XF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "")

(define_expand "cmpdf_cc"
  [(parallel [(set (cc0)
		   (compare (match_operand:DF 0 "register_operand" "")
			    (match_operand:DF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "")

(define_expand "cmpdf_ccfpeq"
  [(parallel [(set (cc0)
		   (compare:CCFPEQ (match_operand:DF 0 "register_operand" "")
				   (match_operand:DF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "
{
  if (! register_operand (operands[1], DFmode))
    operands[1] = copy_to_mode_reg (DFmode, operands[1]);
}")

(define_expand "cmpsf_cc"
  [(parallel [(set (cc0)
		   (compare (match_operand:SF 0 "register_operand" "")
			    (match_operand:SF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "")

(define_expand "cmpsf_ccfpeq"
  [(parallel [(set (cc0)
		   (compare:CCFPEQ (match_operand:SF 0 "register_operand" "")
				   (match_operand:SF 1 "register_operand" "")))
	      (clobber (match_scratch:HI 2 ""))])]
  "TARGET_80387"
  "
{
  if (! register_operand (operands[1], SFmode))
    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
}")

;; logical compare

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "general_operand" "%ro")
		(match_operand:SI 1 "nonmemory_operand" "ri")))]
  ""
  "*
{
  /* For small integers, we may actually use testb. */
  if (GET_CODE (operands[1]) == CONST_INT
      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
      && (! REG_P (operands[0]) || QI_REG_P (operands[0]))
      /* A Pentium test is pairable only with eax. Not with ah or al.  */
      && (! REG_P (operands[0]) || REGNO (operands[0]) || !TARGET_PENTIUM
          || optimize_size))
    {
      /* We may set the sign bit spuriously.  */

      if ((INTVAL (operands[1]) & ~0xff) == 0)
        {
	  cc_status.flags |= CC_NOT_NEGATIVE;
	  return AS2 (test%B0,%1,%b0);
	}

      if ((INTVAL (operands[1]) & ~0xff00) == 0)
        {
	  cc_status.flags |= CC_NOT_NEGATIVE;
	  operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);

	  if (QI_REG_P (operands[0]))
	    return AS2 (test%B0,%1,%h0);
	  else
	    {
	      operands[0] = adj_offsettable_operand (operands[0], 1);
	      return AS2 (test%B0,%1,%b0);
	    }
	}

      if (GET_CODE (operands[0]) == MEM
	  && (INTVAL (operands[1]) & ~0xff0000) == 0)
        {
	  cc_status.flags |= CC_NOT_NEGATIVE;
	  operands[1] = GEN_INT (INTVAL (operands[1]) >> 16);
	  operands[0] = adj_offsettable_operand (operands[0], 2);
	  return AS2 (test%B0,%1,%b0);
	}

      if (GET_CODE (operands[0]) == MEM
	  && (INTVAL (operands[1]) & ~0xff000000) == 0)
        {
	  operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff);
	  operands[0] = adj_offsettable_operand (operands[0], 3);
	  return AS2 (test%B0,%1,%b0);
	}
    }

  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
    return AS2 (test%L0,%1,%0);

  return AS2 (test%L1,%0,%1);
}"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (cc0)
	(and:HI (match_operand:HI 0 "general_operand" "%ro")
		(match_operand:HI 1 "nonmemory_operand" "ri")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT
      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
      && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
    {
      if ((INTVAL (operands[1]) & 0xff00) == 0)
	{
	  /* ??? This might not be necessary. */
	  if (INTVAL (operands[1]) & 0xffff0000)
	    operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);

	  /* We may set the sign bit spuriously.  */
	  cc_status.flags |= CC_NOT_NEGATIVE;
	  return AS2 (test%B0,%1,%b0);
	}

      if ((INTVAL (operands[1]) & 0xff) == 0)
        {
	  operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff);

	  if (QI_REG_P (operands[0]))
	    return AS2 (test%B0,%1,%h0);
	  else
	    {
	      operands[0] = adj_offsettable_operand (operands[0], 1);
	      return AS2 (test%B0,%1,%b0);
	    }
	}
    }

  /* use 32-bit test instruction if there are no sign issues */
  if (GET_CODE (operands[1]) == CONST_INT
      && !(INTVAL (operands[1]) & ~0x7fff)
      && i386_aligned_p (operands[0]))
    return AS2 (test%L0,%1,%k0);

  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
    return AS2 (test%W0,%1,%0);

  return AS2 (test%W1,%0,%1);
}"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (cc0)
	(and:QI (match_operand:QI 0 "nonimmediate_operand" "%qm")
		(match_operand:QI 1 "nonmemory_operand" "qi")))]
  ""
  "*
{
  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
    return AS2 (test%B0,%1,%0);

  return AS2 (test%B1,%0,%1);
}"
  [(set_attr "type" "compare")])

;; move instructions.
;; There is one for each machine mode,
;; and each is preceded by a corresponding push-insn pattern
;; (since pushes are not general_operands on the 386).

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<")