i960.h

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    {								\
      warning ("conflicting architectures defined - using C series", 0); \
      target_flags &= ~TARGET_FLAG_K_SERIES;			\
    }								\
  if (TARGET_K_SERIES && TARGET_MC)				\
    {								\
      warning ("conflicting architectures defined - using K series", 0); \
      target_flags &= ~TARGET_FLAG_MC;				\
    }								\
  if (TARGET_C_SERIES && TARGET_MC)				\
    {								\
      warning ("conflicting architectures defined - using C series", 0);\
      target_flags &= ~TARGET_FLAG_MC;				\
    }								\
  if (TARGET_IC_COMPAT3_0)					\
    {								\
      flag_short_enums = 1;					\
      flag_signed_char = 1;					\
      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
      if (TARGET_IC_COMPAT2_0)					\
	{							\
	  warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
	  target_flags &= ~TARGET_FLAG_IC_COMPAT2_0;		\
	}							\
    }								\
  if (TARGET_IC_COMPAT2_0)					\
    {								\
      flag_signed_char = 1;					\
      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
    }								\
  /* ??? See the LONG_DOUBLE_TYPE_SIZE definition below.  */	\
  if (TARGET_LONG_DOUBLE_64)					\
    warning ("The -mlong-double-64 option does not work yet.", 0);\
  i960_initialize ();						\
}

/* Don't enable anything by default.  The user is expected to supply a -mARCH
   option.  If none is given, then -mka is added by CC1_SPEC.  */
#define TARGET_DEFAULT 0

/* Target machine storage layout.  */

/* Define for cross-compilation from a host with a different float format
   or endianness, as well as to support 80 bit long doubles on the i960.  */
#define REAL_ARITHMETIC

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.
   The i960 case be either big endian or little endian.  We only support
   little endian, which is the most common.  */
#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is lowest
   numbered.  */
#define WORDS_BIG_ENDIAN 0

/* Number of bits in an addressable storage unit.  */
#define BITS_PER_UNIT 8

/* Bitfields cannot cross word boundaries.  */
#define BITFIELD_NBYTES_LIMITED 1

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a pointer.  See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Width in bits of a long double.  Define to 96, and let
   ROUND_TYPE_ALIGN adjust the alignment for speed. */
#define	LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)

/* ??? This must be a constant, because real.c and real.h test it with #if.  */
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE 96

/* Define this to set long double type size to use in libgcc2.c, which can
   not depend on target_flags.  */
#if defined(__LONG_DOUBLE_64__)
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#else
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
#endif

/* Allocation boundary (in *bits*) for storing pointers in memory.  */
#define POINTER_BOUNDARY 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 128

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 128

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* This makes zero-length anonymous fields lay the next field
   at a word boundary.  It also makes the whole struct have
   at least word alignment if there are any bitfields at all.  */
#define PCC_BITFIELD_TYPE_MATTERS 1

/* Every structure's size must be a multiple of this.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* No data type wants to be aligned rounder than this.
   Extended precision floats gets 4-word alignment.  */
#define BIGGEST_ALIGNMENT 128

/* Define this if move instructions will actually fail to work
   when given unaligned data.
   80960 will work even with unaligned data, but it is slow.  */
#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN

/* Specify alignment for string literals (which might be higher than the
   base type's minimal alignment requirement.  This allows strings to be
   aligned on word boundaries, and optimizes calls to the str* and mem*
   library functions.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
  (TREE_CODE (EXP) == STRING_CST	\
   && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
   ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP)))	    \
   : (ALIGN))

/* Make XFmode floating point quantities be 128 bit aligned.  */
#define DATA_ALIGNMENT(TYPE, ALIGN)					\
  (TREE_CODE (TYPE) == ARRAY_TYPE					\
   && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode				\
   && (ALIGN) < 128 ? 128 : (ALIGN))

/* Macros to determine size of aggregates (structures and unions
   in C).  Normally, these may be defined to simply return the maximum
   alignment and simple rounded-up size, but on some machines (like
   the i960), the total size of a structure is based on a non-trivial
   rounding method.  */

#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED)		\
  ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode)	   \
   ? 128  /* Put 80 bit floating point elements on 128 bit boundaries.  */ \
   : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE)				   \
       && TREE_CODE (TYPE) == RECORD_TYPE)				   \
      ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
      : MAX ((COMPUTED), (SPECIFIED))))

#define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED)		\
  ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode)	\
   ? build_int_2 (128, 0) : round_up (COMPUTED, SPECIFIED))

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   Registers 0-15 are the global registers (g0-g15).
   Registers 16-31 are the local registers (r0-r15).
   Register 32-35 are the fp registers (fp0-fp3).
   Register 36 is the condition code register.
   Register 37 is unused.  */

#define FIRST_PSEUDO_REGISTER 38

/* 1 for registers that have pervasive standard uses and are not available
   for the register allocator.  On 80960, this includes the frame pointer
   (g15), the previous FP (r0), the stack pointer (r1), the return
   instruction pointer (r2), and the argument pointer (g14).  */
#define FIXED_REGISTERS  \
 {0, 0, 0, 0, 0, 0, 0, 0,	\
  0, 0, 0, 0, 0, 0, 1, 1,	\
  1, 1, 1, 0, 0, 0, 0, 0,	\
  0, 0, 0, 0, 0, 0, 0, 0,	\
  0, 0, 0, 0, 1, 1}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */

/* On the 80960, note that:
	g0..g3 are used for return values,
	g0..g7 may always be used for parameters,
	g8..g11 may be used for parameters, but are preserved if they aren't,
	g12 is the static chain if needed, otherwise is preserved
	g13 is the struct return ptr if used, or temp, but may be trashed,
	g14 is the leaf return ptr or the arg block ptr otherwise zero,
		must be reset to zero before returning if it was used,
	g15 is the frame pointer,
	r0 is the previous FP,
	r1 is the stack pointer,
	r2 is the return instruction pointer,
	r3-r15 are always available,
	r3 is clobbered by calls in functions that use the arg pointer
	r4-r11 may be clobbered by the mcount call when profiling
	r4-r15 if otherwise unused may be used for preserving global registers
	fp0..fp3 are never available.  */
#define CALL_USED_REGISTERS  \
 {1, 1, 1, 1, 1, 1, 1, 1,	\
  0, 0, 0, 0, 0, 1, 1, 1,	\
  1, 1, 1, 0, 0, 0, 0, 0,	\
  0, 0, 0, 0, 0, 0, 0, 0,	\
  1, 1, 1, 1, 1, 1}

/* If no fp unit, make all of the fp registers fixed so that they can't
   be used.  */
#define	CONDITIONAL_REGISTER_USAGE	\
  if (! TARGET_NUMERICS) {						\
     fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
  }									\

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On 80960, ordinary registers hold 32 bits worth, but can be ganged
   together to hold double or extended precision floating point numbers,
   and the floating point registers hold any size floating point number */
#define HARD_REGNO_NREGS(REGNO, MODE)   \
  ((REGNO) < 32							\
   ? (((MODE) == VOIDmode)					\
      ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
   : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On 80960, the cpu registers can hold any mode but the float registers
   can only hold SFmode, DFmode, or XFmode.  */
extern int hard_regno_mode_ok ();
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */

#define MODES_TIEABLE_P(MODE1, MODE2) \
  ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* 80960 pc isn't overloaded on a register that the compiler knows about.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 17

/* Actual top-of-stack address is same as
   the contents of the stack pointer register.  */
#define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 15

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
/* ??? It isn't clear to me why this is here.  Perhaps because of a bug (since
   fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
   caused this to fail.  */
/* ??? Must check current_function_has_nonlocal_goto, otherwise frame pointer
   elimination messes up nonlocal goto sequences.  I think this works for other
   targets because they use indirect jumps for the return which disables fp
   elimination.  */
#define FRAME_POINTER_REQUIRED \
  (! leaf_function_p () || current_function_has_nonlocal_goto)

/* C statement to store the difference between the frame pointer
   and the stack pointer values immediately after the function prologue.

   Since the stack grows upward on the i960, this must be a negative number.
   This includes the 64 byte hardware register save area and the size of
   the frame.  */

#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
  do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM 14

/* Register in which static-chain is passed to a function.
   On i960, we use g12.  We can't use any local register, because we need
   a register that can be set before a call or before a jump.  */
#define STATIC_CHAIN_REGNUM 12
 
/* Functions which return large structures get the address
   to place the wanted value at in g13.  */

#define STRUCT_VALUE_REGNUM 13 

/* The order in which to allocate registers.  */

#define	REG_ALLOC_ORDER	\
{  4, 5, 6, 7, 0, 1, 2, 3, 13,	 /* g4, g5, g6, g7, g0, g1, g2, g3, g13  */ \
  20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11  */    \
  28, 29, 30, 31, 19, 8, 9, 10,	 /* r12, r13, r14, r15, r3, g8, g9, g10  */ \
  11, 12,			 /* g11, g12  */			    \
  32, 33, 34, 35,		 /* fp0, fp1, fp2, fp3  */		    \
  /* We can't actually allocate these.  */				    \
  16, 17, 18, 14, 15, 36, 37}	 /* r0, r1, r2, g14, g15, cc  */

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.