tahoe.md

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  if (rtx_equal_p (operands[1], operands[2]))
    return \"clrb %0\";
  return \"subb3 %2,%1,%0\";
}")


; subsf3 can only subtract into the fpp accumulator due to the way
; the fpp reg is limited by the instruction set.  This also doesn't
; bother setting up flags.

(define_insn "subsf3"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(minus:SF (match_operand:SF 1 "register_operand" "0")
		  (match_operand:SF 2 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"subf %2\";
}")


; subdf3 is set up to subtract into the fpp reg due to limitations
; of the fpp instruction set.  Doubles can not be immediate.  This
; instruction does not set the flags.

(define_insn "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=a")
	(minus:DF (match_operand:DF 1 "register_operand" "0")
		  (match_operand:DF 2 "general_operand" "rm")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"subd %2\";
}")


(define_insn "mulsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(mult:SI (match_operand:SI 1 "general_operand" "g")
		 (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"mull2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"mull2 %1,%0\";
  return \"mull3 %1,%2,%0\";
}")


; mulsf3 can only multiply into the fpp accumulator due to limitations
; of the fpp.  It also does not set the condition codes properly.

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(mult:SF (match_operand:SF 1 "register_operand" "%0")
		 (match_operand:SF 2 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"mulf %2\";
}")


; muldf3 can only multiply into the fpp reg since the fpp is limited
; from the rest.  Doubles may not be immediate mode.  This does not set
; the flags like gcc would expect.

(define_insn "muldf3"
  [(set (match_operand:DF 0 "register_operand" "=a")
	(mult:DF (match_operand:DF 1 "register_operand" "%0")
		 (match_operand:DF 2 "general_operand" "rm")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"muld %2\";
}")



(define_insn "divsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(div:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[1], operands[2]))
    return \"movl $1,%0\";
  if (operands[1] == const0_rtx)
    return \"clrl %0\";
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) == -1)
    return \"mnegl %1,%0\";
  if (rtx_equal_p (operands[0], operands[1]))
    return \"divl2 %2,%0\";
  return \"divl3 %2,%1,%0\";
}")


; divsf3 must divide into the fpp accumulator.  Flags are not set by
; this instruction, so they are cleared.

(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(div:SF (match_operand:SF 1 "register_operand" "0")
		(match_operand:SF 2 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"divf %2\";
}")


; divdf3 also must divide into the fpp reg so optimization isn't
; possible.  Note that doubles cannot be immediate.  The flags here
; are not set correctly so they must be ignored.

(define_insn "divdf3"
  [(set (match_operand:DF 0 "register_operand" "=a")
	(div:DF (match_operand:DF 1 "register_operand" "0")
		(match_operand:DF 2 "general_operand" "rm")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"divd %2\";
}")



(define_insn "andsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(and:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"andl2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"andl2 %1,%0\";
  return \"andl3 %2,%1,%0\";
}")



(define_insn "andhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(and:HI (match_operand:HI 1 "general_operand" "g")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"andw2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"andw2 %1,%0\";
  return \"andw3 %2,%1,%0\";
}")


(define_insn "andqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(and:QI (match_operand:QI 1 "general_operand" "g")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"andb2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"andb2 %1,%0\";
  return \"andb3 %2,%1,%0\";
}")


(define_insn "iorsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ior:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"orl2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"orl2 %1,%0\";
  return \"orl3 %2,%1,%0\";
}")



(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(ior:HI (match_operand:HI 1 "general_operand" "g")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"orw2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"orw2 %1,%0\";
  return \"orw3 %2,%1,%0\";
}")



(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(ior:QI (match_operand:QI 1 "general_operand" "g")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"orb2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"orb2 %1,%0\";
  return \"orb3 %2,%1,%0\";
}")


(define_insn "xorsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(xor:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"xorl2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"xorl2 %1,%0\";
  return \"xorl3 %2,%1,%0\";
}")


(define_insn "xorhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(xor:HI (match_operand:HI 1 "general_operand" "g")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"xorw2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"xorw2 %1,%0\";
  return \"xorw3 %2,%1,%0\";
}")


(define_insn "xorqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(xor:QI (match_operand:QI 1 "general_operand" "g")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (rtx_equal_p (operands[0], operands[1]))
    return \"xorb2 %2,%0\";
  if (rtx_equal_p (operands[0], operands[2]))
    return \"xorb2 %1,%0\";
  return \"xorb3 %2,%1,%0\";
}")


; shifts on the tahoe are expensive, try some magic first...

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ashift:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE(operands[2]) == REG)
      return \"mull3 ___shtab[%2],%1,%0\";
  /* if (GET_CODE(operands[2]) == REG)
    if (rtx_equal_p (operands[0], operands[1]))
      return \"mull2 ___shtab[%2],%1\";
    else
      return \"mull3 ___shtab[%2],%1,%0\"; */
  if (GET_CODE(operands[1]) == REG)
    {
      if (operands[2] == const1_rtx)
	{
	  CC_STATUS_INIT;
	  return \"movaw 0[%1],%0\";
	}
      if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
	{
	  CC_STATUS_INIT;
	  return \"moval 0[%1],%0\";
	}
    }
  if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
    return \"shal %2,%1,%0\";
  if (rtx_equal_p (operands[0], operands[1]))
    return \"mull2 %s2,%1\";
  else
    return \"mull3 %s2,%1,%0\";
}")


(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "shar %2,%1,%0")


; shifts are very expensive, try some magic first...

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "shrl %2,%1,%0")


(define_insn "negsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "mnegl %1,%0")


(define_insn "neghi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "mnegw %1,%0")


(define_insn "negqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "mnegb %1,%0")


; negsf2 can only negate the value already in the fpp accumulator.
; The value remains in the fpp accumulator.  No flags are set.

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=a,=a")
	(neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  switch (which_alternative)
    {
    case 0: return \"negf\";
    case 1: return \"lnf %1\";
    }
}")


; negdf2 can only negate the value already in the fpp accumulator.
; The value remains in the fpp accumulator.  No flags are set.

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=a,=a")
	(neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  switch (which_alternative)
    {
    case 0: return \"negd\";
    case 1: return \"lnd %1\";
    }
}")


; sqrtsf2 tahoe can calculate the square root of a float in the
; fpp accumulator.  The answer remains in the fpp accumulator.  No
; flags are set by this function.

(define_insn "sqrtsf2"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"sqrtf\";
}")


; ffssi2 tahoe instruction gives one less than gcc desired result for
; any given input.  So the increment is necessary here.

(define_insn "ffssi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ffs:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "*
{
  if (push_operand(operands[0], SImode))
    return \"ffs %1,%0\;incl (sp)\";
  return \"ffs %1,%0\;incl %0\";
}")


(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(not:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "mcoml %1,%0")


(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(not:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "mcomw %1,%0")


(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(not:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "mcomb %1,%0")


; cmpsi works fine, but due to microcode problems, the tahoe doesn't
; properly compare hi's and qi's.  Leaving them out seems to be acceptable
; to the compiler, so they were left out.  Compares of the stack are
; possible, though.

; There are optimized cases possible, however.  These follow first.

(define_insn ""
  [(set (cc0)
	(compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
		 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
  ""
  "cmpw %0,%1")

(define_insn ""
  [(set (cc0)
	(compare (match_operand:SI 0 "nonmemory_operand" "ri")
		 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
  ""
  "cmpw %0,%1")

(define_insn ""
  [(set (cc0)
	(compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
		 (match_operand:SI 1 "nonmemory_operand" "ri")))]
  ""
  "cmpw %0,%1")

; zero-extended compares give the same result as sign-extended compares, if
; the compare is unsigned.  Just see: if both operands are <65536 they are the
; same in both cases.  If both are >=65536 the you effectively compare x+D
; with y+D, where D=2**32-2**16, so the result is the same.  if x<65536 and
; y>=65536 then you compare x with y+D, and in both cases the result is x<y.

(define_insn ""
  [(set (cc0)
	(compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
		 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
  "tahoe_cmp_check (insn, operands[0], 0)"
  "cmpw %0,%1")

(define_insn ""
  [(set (cc0)
	(compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
		 (match_operand:SI 1 "immediate_operand" "i")))]
  "tahoe_cmp_check(insn, operands[1], 65535)"
  "*
{
  if (INTVAL (operands[1]) > 32767)
    operands[1] = GEN_INT (INTVAL (operands[1]) + 0xffff0000);
  return \"cmpw %0,%1\";
}")


(define_insn ""
  [(set (cc0)
	(compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
		 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
  ""
  "cmpb %0,%1")

(define_insn ""
  [(set (cc0)
	(compare (match_operand:SI 0 "nonmemory_operand" "ri")
		 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
  ""
  "cmpb %0,%1")

(define_insn ""
  [(set (cc0)
	(compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
		 (match_operand:SI 1 "nonmemory_operand" "ri")))]
  ""
  "cmpb %0,%1")

; zero-extended compares give the same result as sign-extended compares, if
; the compare is unsigned.  Just see: if both operands are <128 they are the
; same in both cases.  If both are >=128 the you effectively compare x+D
; with y+D, where D=2**32-2**8, so the result is the same.  if x<128 and
; y>=128 then you compare x with y+D, and in both cases the result is x<y.

(define_insn ""
  [(set (cc0)
	(compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
		 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
  "tahoe_cmp_check (insn, operands[0], 0)"
  "cmpb %0,%1")

(define_insn ""
  [(set (cc0)