c4x.h

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/* Definitions of target machine for GNU compiler.  TMS320C[34]x
   Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.

   Contributed by Michael Hayes ([e-mail])
              and Herman Ten Brugge ([e-mail]).

   This file is part of GNU CC.

   GNU CC is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 1, or (at your option)
   any later version.

   GNU CC is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GNU CC; see the file COPYING.  If not, write to
   the Free Software Foundation, 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

/* Set the following so that some of the macros expand to function
   calls to simplify debugging.  */
#define C4X_DEBUG 1

/* RUN-TIME TARGET SPECIFICATION */

#define C4x   1

/* Name of the c4x assembler */

#define ASM_PROG "c4x-as"

/* Name of the c4x linker */

#define LD_PROG "c4x-ld"

/* Define assembler options */

#define ASM_SPEC "\
%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
%{!m30:%{!m40:-m40}}}}}}} \
%{mcpu=30:-m30} \
%{mcpu=31:-m31} \
%{mcpu=32:-m32} \
%{mcpu=40:-m40} \
%{mcpu=44:-m44} \
%{m30:-m30} \
%{m31:-m31} \
%{m32:-m32} \
%{m40:-m40} \
%{m44:-m44} \
%{mmemparm:-p} %{mregparm:-r} \
%{!mmemparm:%{!mregparm:-r}} \
%{mbig:-b} %{msmall:-s} \
%{!msmall:%{!mbig:-b}}"

/* Define linker options */

#define LINK_SPEC "\
%{m30:--architecture c3x} \
%{m31:--architecture c3x} \
%{m32:--architecture c3x} \
%{mcpu=30:--architecture c3x} \
%{mcpu=31:--architecture c3x} \
%{mcpu=32:--architecture c3x}"

/* Define C preprocessor options.  */

#define CPP_SPEC "\
%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
  %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
%{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
%{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
%{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
%{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
%{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
%{!mmemparm:%{!mregparm:-D_REGPARM }} \
%{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
%{!msmall:%{!mbig:-D_BIGMODEL }} \
%{finline-functions:-D_INLINE }"

/* Specify the startup file to link with.  */

#define STARTFILE_SPEC "\
%{!mmemparm:%{m30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{m30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{m31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{m31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{m32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{m32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{mcpu=30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{mcpu=30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{mcpu=31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{mcpu=31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{mcpu=32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
%{mmemparm:%{mcpu=32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
%{!mmemparm:%{m40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
%{mmemparm:%{m40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
%{!mmemparm:%{m44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
%{mmemparm:%{m44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
%{!mmemparm:%{mcpu=40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
%{mmemparm:%{mcpu=40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
%{!mmemparm:%{mcpu=44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
%{mmemparm:%{mcpu=44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
%{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sr%O%s}}}}}}}}}}}} \
%{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sm%O%s}}}}}}}}}}}} \
%{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4br%O%s}}}}}}}}}}}} \
%{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4bm%O%s}}}}}}}}}}}}"

/* Specify the end file to link with */

#define ENDFILE_SPEC ""

/* Target compilation option flags */

#define SMALL_MEMORY_FLAG   0x0000001 /* small memory model */
#define MPYI_FLAG           0x0000002 /* use 24-bit MPYI for C3x */
#define FAST_FIX_FLAG       0x0000004 /* fast fixing of floats */
#define RPTS_FLAG           0x0000008 /* allow use of RPTS */
#define C3X_FLAG            0x0000010 /* emit C3x code */
#define TI_FLAG             0x0000020 /* be compatible with TI assembler */
#define PARANOID_FLAG       0x0000040 /* be paranoid about DP reg. in ISRs */
#define MEMPARM_FLAG        0x0000080 /* pass arguments on stack */
#define DEVEL_FLAG          0x0000100 /* enable features under development */
#define RPTB_FLAG           0x0000200 /* enable repeat block */
#define BK_FLAG             0x0000400 /* use BK as general register */
#define DB_FLAG             0x0000800 /* use decrement and branch for C3x */
#define DEBUG_FLAG          0x0001000 /* enable debugging of GCC */
#define HOIST_FLAG          0x0002000 /* force constants into registers */
#define LOOP_UNSIGNED_FLAG  0x0004000 /* allow unsigned loop counters */
#define FORCE_FLAG          0x0008000 /* force op0 and op1 to be same */
#define PRESERVE_FLOAT_FLAG 0x0010000 /* save all 40 bits for floats */
#define PARALLEL_PACK_FLAG  0x0020000 /* allow parallel insn packing */
#define PARALLEL_MPY_FLAG   0x0040000 /* allow MPY||ADD, MPY||SUB insns */
#define ALIASES_FLAG	    0x0080000 /* assume mem refs possibly aliased */

#define C30_FLAG            0x0100000 /* emit C30 code */
#define C31_FLAG            0x0200000 /* emit C31 code */
#define C32_FLAG            0x0400000 /* emit C32 code */
#define C40_FLAG            0x1000000 /* emit C40 code */
#define C44_FLAG            0x2000000 /* emit C44 code */

/* Run-time compilation parameters selecting different hardware subsets.

   Macro to define tables used to set the flags.
   This is a list in braces of triplets in braces,
   each pair being { "NAME", VALUE, "DESCRIPTION" }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES \
{ { "small", SMALL_MEMORY_FLAG, \
    "Small memory model" }, \
  { "big", -SMALL_MEMORY_FLAG, \
    "Big memory model" }, \
  { "mpyi", MPYI_FLAG, \
    "Use MPYI instruction for C3x" }, \
  { "no-mpyi", -MPYI_FLAG, \
    "Do not use MPYI instruction for C3x" }, \
  { "fast-fix", FAST_FIX_FLAG, \
    "Use fast but approximate float to integer conversion" }, \
  { "no-fast-fix", -FAST_FIX_FLAG, \
    "Use slow but accurate float to integer conversion" }, \
  { "rpts", RPTS_FLAG, \
    "Enable use of RTPS instruction" }, \
  { "no-rpts", -RPTS_FLAG, \
    "Disable use of RTPS instruction" }, \
  { "rptb", RPTB_FLAG, \
    "Enable use of RTPB instruction" }, \
  { "no-rptb", -RPTB_FLAG, \
    "Disable use of RTPB instruction" }, \
  { "30", C30_FLAG, \
    "Generate code for C30 CPU"}, \
  { "31", C31_FLAG, \
    "Generate code for C31 CPU"}, \
  { "32", C32_FLAG, \
    "Generate code for C32 CPU"}, \
  { "40", C40_FLAG, \
    "Generate code for C40 CPU"}, \
  { "44", C44_FLAG, \
    "Generate code for C44 CPU"}, \
  { "ti", TI_FLAG, \
    "Emit code compatible with TI tools"}, \
  { "no-ti", -TI_FLAG, \
    "Emit code to use GAS extensions"}, \
  { "paranoid", PARANOID_FLAG, \
    "Save DP across ISR in small memory model" }, \
  { "no-paranoid", -PARANOID_FLAG, \
    "Don't save DP across ISR in small memory model" }, \
  { "isr-dp-reload", PARANOID_FLAG, \
    "Save DP across ISR in small memory model" }, \
  { "no-isr-dp-reload", -PARANOID_FLAG, \
    "Don't save DP across ISR in small memory model" }, \
  { "memparm", MEMPARM_FLAG, \
    "Pass arguments on the stack" }, \
  { "regparm", -MEMPARM_FLAG,  \
    "Pass arguments in registers" }, \
  { "devel", DEVEL_FLAG, \
    "Enable new features under development" }, \
  { "no-devel", -DEVEL_FLAG, \
    "Disable new features under development" }, \
  { "bk", BK_FLAG, \
    "Use the BK register as a general purpose register" }, \
  { "no-bk", -BK_FLAG, \
    "Do not allocate BK register" }, \
  { "db", DB_FLAG, \
    "Enable use of DB instruction" }, \
  { "no-db", -DB_FLAG, \
    "Disable use of DB instruction" }, \
  { "debug", DEBUG_FLAG, \
    "Enable debugging" }, \
  { "no-debug", -DEBUG_FLAG, \
    "Disable debugging" }, \
  { "hoist", HOIST_FLAG, \
    "Force constants into registers to improve hoisting" }, \
  { "no-hoist", -HOIST_FLAG, \
    "Don't force constants into registers" }, \
  { "force", FORCE_FLAG, \
    "Force RTL generation to emit valid 3 operand insns" }, \
  { "no-force", -FORCE_FLAG, \
    "Allow RTL generation to emit invalid 3 operand insns" }, \
  { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
    "Allow unsigned interation counts for RPTB/DB" }, \
  { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
    "Disallow unsigned iteration counts for RPTB/DB" }, \
  { "preserve-float", PRESERVE_FLOAT_FLAG, \
    "Preserve all 40 bits of FP reg across call" }, \
  { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
    "Only preserve 32 bits of FP reg across call" }, \
  { "parallel-insns", PARALLEL_PACK_FLAG, \
    "Enable parallel instructions" }, \
  { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
    "Disable parallel instructions" }, \
  { "parallel-mpy", PARALLEL_MPY_FLAG, \
    "Enable MPY||ADD and MPY||SUB instructions" }, \
  { "no-parallel-insns", -PARALLEL_PACK_FLAG, \
    "Disable MPY||ADD and MPY||SUB instructions" }, \
  { "aliases", ALIASES_FLAG, \
    "Assume that pointers may be aliased" }, \
  { "no-aliases", -ALIASES_FLAG, \
    "Assume that pointers not aliased" }, \
  { "", TARGET_DEFAULT, ""} }

/* Default target switches */

/* Play safe, not the fastest code.  */
#define TARGET_DEFAULT		ALIASES_FLAG | PARALLEL_PACK_FLAG \
				| PARALLEL_MPY_FLAG | RPTB_FLAG

/* Caveats:
   Max iteration count for RPTB/RPTS is 2^31 + 1.
   Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
   RPTS blocks interrupts.  */


extern int target_flags;

#define TARGET_INLINE		1 /* Inline MPYI */
#define TARGET_PARALLEL	        1 /* Enable parallel insns in MD */
#define TARGET_SMALL_REG_CLASS	0

#define TARGET_SMALL		(target_flags & SMALL_MEMORY_FLAG)
#define TARGET_MPYI		(!TARGET_C3X || (target_flags & MPYI_FLAG))
#define TARGET_FAST_FIX		(target_flags & FAST_FIX_FLAG)
#define TARGET_RPTS		(target_flags & RPTS_FLAG)
#define TARGET_TI		(target_flags & TI_FLAG)
#define TARGET_PARANOID		(target_flags & PARANOID_FLAG)
#define TARGET_MEMPARM		(target_flags & MEMPARM_FLAG)
#define TARGET_DEVEL		(target_flags & DEVEL_FLAG)
#define TARGET_RPTB		(target_flags & RPTB_FLAG \
				 && optimize >= 2)
#define TARGET_BK		(target_flags & BK_FLAG)
#define TARGET_DB		(! TARGET_C3X || (target_flags & DB_FLAG))
#define TARGET_DEBUG		(target_flags & DEBUG_FLAG)
#define TARGET_HOIST		(target_flags & HOIST_FLAG)
#define TARGET_LOOP_UNSIGNED	(target_flags & LOOP_UNSIGNED_FLAG)
#define TARGET_FORCE		(target_flags & FORCE_FLAG)
#define	TARGET_PRESERVE_FLOAT	(target_flags & PRESERVE_FLOAT_FLAG)
#define TARGET_PARALLEL_PACK	(TARGET_RPTB \
				 && (target_flags & PARALLEL_PACK_FLAG) \
				 && optimize >= 2)
#define TARGET_PARALLEL_MPY	(TARGET_PARALLEL_PACK \
				 && (target_flags & PARALLEL_MPY_FLAG))
#define	TARGET_ALIASES		(target_flags & ALIASES_FLAG)

#define TARGET_C3X		(target_flags & C3X_FLAG)
#define TARGET_C30		(target_flags & C30_FLAG)
#define TARGET_C31		(target_flags & C31_FLAG)
#define TARGET_C32		(target_flags & C32_FLAG)
#define TARGET_C40		(target_flags & C40_FLAG)
#define TARGET_C44		(target_flags & C44_FLAG)

/* Define some options to control code generation.  */
#define TARGET_LOAD_ADDRESS	(1 || (! TARGET_C3X && ! TARGET_SMALL))
#define TARGET_EXPOSE_LDP	0

/* -mrpts            allows the use of the RPTS instruction irregardless.
   -mrpts=max-cycles will use RPTS if the number of cycles is constant
   and less than max-cycles.  */

#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)

#define	BCT_CHECK_LOOP_ITERATIONS  !(TARGET_LOOP_UNSIGNED)

/* -mcpu=XX    with XX = target DSP version number */

/* This macro is similar to `TARGET_SWITCHES' but defines names of
   command options that have values.  Its definition is an
   initializer with a subgrouping for each command option.

   Each subgrouping contains a string constant, that defines the
   fixed part of the option name, and the address of a variable.
   The variable, type `char *', is set to the variable part of the
   given option if the fixed part matches.  The actual option name
   is made by appending `-m' to the specified name.

   Here is an example which defines `-mshort-data-NUMBER'.  If the
   given option is `-mshort-data-512', the variable `m88k_short_data'
   will be set to the string `"512"'.

   extern char *m88k_short_data;
   #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */

extern char *c4x_rpts_cycles_string, *c4x_cpu_version_string;

#define TARGET_OPTIONS		\
{ {"rpts=", &c4x_rpts_cycles_string, \
   "Specify maximum number of iterations for RPTS" }, \
  {"cpu=", &c4x_cpu_version_string, \
   "Select CPU to generate code for" } }

/* Sometimes certain combinations of command options do not make sense
   on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.  */

extern void c4x_override_options ();
#define OVERRIDE_OPTIONS c4x_override_options ()

/* Define this to change the optimizations performed by default.  */
extern void c4x_optimization_options ();
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL,SIZE)

/* Run Time Target Specification  */

#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)" );

/* Storage Layout  */

#define BITS_BIG_ENDIAN		0
#define BYTES_BIG_ENDIAN	0
#define WORDS_BIG_ENDIAN	0

/* Technically, we are little endian, but we put the floats out as