c4x.md

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  ""
  "pop\\t%0"
  [(set_attr "type" "pop")])

;
; ABSI
;
(define_expand "absqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (abs:QI (match_operand:QI 1 "src_operand" "")))
              (clobber (reg:CC_NOOV 21))])]
  ""
  "")

(define_insn "*absqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (abs:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
   (clobber (reg:CC_NOOV 21))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "int16,int16")])

(define_insn "*absqi2_test"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

(define_insn "*absqi2_set"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")
        (abs:QI (match_dup 1)))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

;
; NEGI
;
(define_expand "negqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (neg:QI (match_operand:QI 1 "src_operand" "")))
              (clobber (reg:CC_NOOV 21))])]
""
"")

(define_insn "*negqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (neg:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
   (clobber (reg:CC_NOOV 21))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "int16,int16")])

(define_insn "*negqi2_test"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

(define_insn "*negqi2_set"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")
        (neg:QI (match_dup 1)))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

(define_insn "*negbqi2_clobber"
  [(set (match_operand:QI 0 "ext_reg_operand" "=d")
        (neg:QI (match_operand:QI 1 "src_operand" "rIm")))
   (use (reg:CC_NOOV 21))
   (clobber (reg:CC_NOOV 21))]
  ""
  "negb\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

;
; NOT
;
(define_expand "one_cmplqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (not:QI (match_operand:QI 1 "lsrc_operand" "")))
              (clobber (reg:CC 21))])]
  ""
  "")

(define_insn "*one_cmplqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (not:QI (match_operand:QI 1 "lsrc_operand" "rLm,rLm")))
   (clobber (reg:CC 21))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "uint16,uint16")])

(define_insn "*one_cmplqi2_test"
  [(set (reg:CC 21)
        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
                    (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "uint16")])

(define_insn "*one_cmplqi2_set"
  [(set (reg:CC 21)
        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
                    (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")        
        (not:QI (match_dup 1)))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "uint16")])        

(define_insn "*one_cmplqi2_const_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (match_operand:QI 1 "not_const_operand" "N,N"))
   (clobber (reg:CC 21))]
  ""
  "@
   not\\t%N1,%0
   not\\t%N1,%0"
   [(set_attr "type" "unarycc,unary")
    (set_attr "data" "not_uint16,not_uint16")])

; movqi can use this for loading an integer that can't normally
; fit into a 16-bit signed integer.  The drawback is that it cannot
; go into R0-R11 since that will clobber the CC and movqi shouldn't
; do that.  This can cause additional reloading but in most cases
; this will cause only an additional register move.  With the large
; memory model we require an extra instruction to load DP anyway,
; if we're loading the constant from memory.  The big advantage of
; allowing constants that satisfy not_const_operand in movqi, is that
; it allows andn to be generated more often.
; However, there is a problem if GCC has decided that it wants
; to use R0-R11, since we won't have a matching pattern...
; In interim, we prevent immed_const allowing `N' constants.
(define_insn "*one_cmplqi2_const_noclobber"
  [(set (match_operand:QI 0 "std_reg_operand" "=c")
        (match_operand:QI 1 "not_const_operand" "N"))]
  ""
  "not\\t%N1,%0"
  [(set_attr "type" "unary")
   (set_attr "data" "not_uint16")])

;
; ROL
;
(define_expand "rotlqi3"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (rotate:QI (match_operand:QI 1 "reg_operand" "")
                              (match_operand:QI 2 "const_int_operand" "")))
              (clobber (reg:CC 21))])]
  ""
  "if (INTVAL (operands[2]) > 4)
     FAIL; /* Open code as two shifts and an or */
   if (INTVAL (operands[2]) > 1)
     {
        int i;
	rtx tmp;

        /* If we have 4 or fewer shifts, then it is probably faster
           to emit separate ROL instructions.  A C3x requires
           at least 4 instructions (a C4x requires at least 3), to
           perform a rotation by shifts.  */

	tmp = operands[1];
        for (i = 0; i < INTVAL (operands[2]) - 1; i++)
	  {
   	    tmp = gen_reg_rtx (QImode);
            emit_insn (gen_rotl_1_clobber (tmp, operands[1]));
	    operands[1] = tmp;
	  }
        emit_insn (gen_rotl_1_clobber (operands[0], tmp));
        DONE;
     }")

(define_insn "rotl_1_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (rotate:QI (match_operand:QI 1 "reg_operand" "0,0")
                   (const_int 1)))
   (clobber (reg:CC 21))]
  ""
  "rol\\t%0"
  [(set_attr "type" "unarycc,unary")])
; Default to int16 data attr.

;
; ROR
;
(define_expand "rotrqi3"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (rotatert:QI (match_operand:QI 1 "reg_operand" "")
                                (match_operand:QI 2 "const_int_operand" "")))
              (clobber (reg:CC 21))])]
  ""
  "if (INTVAL (operands[2]) > 4)
     FAIL; /* Open code as two shifts and an or */
   if (INTVAL (operands[2]) > 1)
     {
        int i;
	rtx tmp;
 
        /* If we have 4 or fewer shifts, then it is probably faster
           to emit separate ROL instructions.  A C3x requires
           at least 4 instructions (a C4x requires at least 3), to
           perform a rotation by shifts.  */
 
	tmp = operands[1];
        for (i = 0; i < INTVAL (operands[2]) - 1; i++)
	  {
   	    tmp = gen_reg_rtx (QImode);
            emit_insn (gen_rotr_1_clobber (tmp, operands[1]));
	    operands[1] = tmp;
	  }
        emit_insn (gen_rotr_1_clobber (operands[0], tmp));
        DONE;
     }")

(define_insn "rotr_1_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (rotatert:QI (match_operand:QI 1 "reg_operand" "0,0")
                     (const_int 1)))
   (clobber (reg:CC 21))]
  ""
  "ror\\t%0"
  [(set_attr "type" "unarycc,unary")])
; Default to int16 data attr.


;
; THREE OPERAND INTEGER INSTRUCTIONS
;

;
; ADDI
;
; This is used by reload when it calls gen_add2_insn for address arithmetic
; so we must emit the pattern that doesn't clobber CC.
;
(define_expand "addqi3"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (plus:QI (match_operand:QI 1 "src_operand" "")
                            (match_operand:QI 2 "src_operand" "")))
              (clobber (reg:CC_NOOV 21))])]
  ""
  "legitimize_operands (PLUS, operands, QImode);
   if (reload_in_progress
       || (! IS_PSEUDO_REGNO (operands[0]) 
           && ! IS_EXT_REG (REGNO (operands[0]))))
   {
      emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
      DONE;
   }")

(define_insn "*addqi3_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
        (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
                 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
   (clobber (reg:CC_NOOV 21))]
  "valid_operands (PLUS, operands, QImode)"
  "@
   addi\\t%2,%0
   addi3\\t%2,%1,%0
   addi3\\t%2,%1,%0
   addi\\t%2,%0
   addi3\\t%2,%1,%0
   addi3\\t%2,%1,%0"
  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
; Default to int16 data attr.

(define_insn "*addqi3_test"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
                                  (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
                         (const_int 0)))
   (clobber (match_scratch:QI 0 "=d,d,d"))]
  "valid_operands (PLUS, operands, QImode)"
  "@
   addi\\t%2,%0
   addi3\\t%2,%1,%0
   addi3\\t%2,%1,%0"
  [(set_attr "type" "binarycc,binarycc,binarycc")])
; Default to int16 data attr.

; gcc does this in combine.c we just reverse it here
(define_insn "*cmp_neg"
  [(set (reg:CC_NOOV 21)
	(compare:CC_NOOV (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
		         (neg: QI (match_operand:QI 2 "src_operand" "g,JR,rS<>"))))
   (clobber (match_scratch:QI 0 "=d,d,d"))]
  "valid_operands (PLUS, operands, QImode)"
  "@
   addi\\t%2,%0
   addi3\\t%2,%1,%0
   addi3\\t%2,%1,%0"
  [(set_attr "type" "binarycc,binarycc,binarycc")])
  
(define_peephole
  [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
                   (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
                            (match_operand:QI 2 "src_operand" "g,JR,rS<>")))
              (clobber (reg:CC_NOOV 21))])
   (set (reg:CC_NOOV 21)
        (compare:CC_NOOV (match_dup 0) (const_int 0)))]
  "valid_operands (PLUS, operands, QImode)"
  "@
   addi\\t%2,%0
   addi3\\t%2,%1,%0
   addi3\\t%2,%1,%0"
  [(set_attr "type" "binarycc