h8300.md

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  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (udiv:HI
	    (match_operand:HI 1 "general_operand" "0")
	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
  ""
  "divxu	%X2,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "clobber")])

;; ??? Will divxu always work here?

(define_insn "divqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (div:HI
	    (match_operand:HI 1 "general_operand" "0")
	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
  ""
  "divxu	%X2,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "clobber")])

(define_insn "udivhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (udiv:SI
	    (match_operand:SI 1 "general_operand" "0")
	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
  "TARGET_H8300H || TARGET_H8300S"
  "divxu.w	%T2,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "clobber")])

(define_insn "divhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (div:SI
	    (match_operand:SI 1 "general_operand" "0")
	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
  "TARGET_H8300H || TARGET_H8300S"
  "divxs.w	%T2,%S0"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

;; ----------------------------------------------------------------------
;; MOD INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "umodqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (umod:HI
	    (match_operand:HI 1 "general_operand" "0")
	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
  ""
  "divxu	%X2,%T0\;mov %t0,%s0"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn "modqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (mod:HI
	    (match_operand:HI 1 "general_operand" "0")
	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
  "TARGET_H8300H || TARGET_H8300S"
  "divxs.b	%X2,%T0\;mov %t0,%s0"
  [(set_attr "length" "6")
   (set_attr "cc" "clobber")])

(define_insn "umodhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (umod:SI
	    (match_operand:SI 1 "general_operand" "0")
	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
  "TARGET_H8300H || TARGET_H8300S"
  "divxu.w	%T2,%S0\;mov %e0,%f0"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn "modhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (mod:SI
	    (match_operand:SI 1 "general_operand" "0")
	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
  "TARGET_H8300H || TARGET_H8300S"
  "divxs.w	%T2,%S0\;mov %e0,%f0"
  [(set_attr "length" "6")
   (set_attr "cc" "clobber")])

;; ----------------------------------------------------------------------
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
  "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
  "@
   and	%X2,%X0
   bclr	%W2,%R0"
  [(set_attr "length" "2,4")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "andqi3"
  [(set (match_operand:QI 0 "bit_operand" "")
	(and:QI (match_operand:QI 1 "bit_operand" "")
		(match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'O', AND))
    DONE;
}")

(define_insn "andhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(and:HI (match_operand:HI 1 "register_operand" "%0")
		(match_operand:HI 2 "nonmemory_operand" "rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if ((i & 0x00ff) != 0x00ff) 
	output_asm_insn (\"and	%s2,%s0\", operands);
      if ((i & 0xff00) != 0xff00) 
	output_asm_insn (\"and	%t2,%t0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"and.w %T2,%T0\";
  return \"and	%s2,%s0\;and	%t2,%t0;\";
}"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%0")
		(match_operand:SI 2 "nonmemory_operand" "rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);
      int upper_cleared, lower_cleared;

      /* The h8300h can't do byte-wise operations on the
	 upper 16bits of 32bit registers.  However, if
	 those bits aren't going to change, or they're
	 going to be zero'd out, then we can work on the
	 low-order bits.  */
      if ((TARGET_H8300H || TARGET_H8300S)
	  && ((i & 0xffff0000) != 0xffff0000
	      || (i & 0xffff0000) == 0x00000000))
        return \"and.l	%S2,%S0\";

      lower_cleared = 0;
      if ((i & 0x0000ffff) == 0x00000000)
	{
	  output_asm_insn (\"sub.w	%f0,%f0\", operands);
	  lower_cleared = 1;
	}

      upper_cleared = 0;
      if ((i & 0xffff0000) == 0x00000000)
	{
	  output_asm_insn (\"sub.w	%e0,%e0\", operands);
	  upper_cleared = 1;
	}

      if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
	output_asm_insn (\"and	%w2,%w0\", operands);
      if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
	output_asm_insn (\"and	%x2,%x0\", operands);
      if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared) 
	output_asm_insn (\"and	%y2,%y0\", operands);
      if ((i & 0xff000000) != 0xff000000 && !upper_cleared) 
	output_asm_insn (\"and	%z2,%z0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"and.l	%S2,%S0\";
  return \"and	%w2,%w0\;and	%x2,%x0\;and	%y2,%y0\;and	%z2,%z0\;\";
}"
  [(set_attr "length" "8")
   (set_attr "cc" "clobber")])


;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
  "@
   or	%X2,%X0
   bset	%V2,%R0"
  [(set_attr "length" "2,4")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "iorqi3"
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'P', IOR))
    DONE;
}")

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=r,r")
	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "J,rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if ((i & 0x00ff) != 0) 
	output_asm_insn (\"or	%s2,%s0\", operands);
      if ((i & 0xff00) != 0) 
	output_asm_insn (\"or	%t2,%t0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"or.w	%T2,%T0\";
  return \"or	%s2,%s0\;or	%t2,%t0; %2 or2\";
}"
  [(set_attr "length" "2,4")
   (set_attr "cc" "clobber,clobber")])

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      /* The h8300h can't do byte-wise operations on the
	 upper 16bits of 32bit registers.  However, if
	 those bits aren't going to change, then we can
	 work on the low-order bits.  */
      if ((TARGET_H8300H || TARGET_H8300S)
	  && (i & 0xffff0000) != 0x00000000)
        return \"or.l	%S2,%S0\";
	
      if ((i & 0x000000ff) != 0) 
	output_asm_insn (\"or	%w2,%w0\", operands);
      if ((i & 0x0000ff00) != 0) 
	output_asm_insn (\"or	%x2,%x0\", operands);
      if ((i & 0x00ff0000) != 0) 
	output_asm_insn (\"or	%y2,%y0\", operands);
      if ((i & 0xff000000) != 0) 
	output_asm_insn (\"or	%z2,%z0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"or.l	%S2,%S0\";
  return \"or	%w2,%w0\;or	%x2,%x0\;or	%y2,%y0\;or	%z2,%z0\;\";
}"
  [(set_attr "length" "2,8")
   (set_attr "cc" "clobber,clobber")])

;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
  "@
   xor	%X2,%X0
   bnot	%V2,%R0"
  [(set_attr "length" "2,4")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "xorqi3"
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'O', XOR))
    DONE;
}")

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "nonmemory_operand" "J,rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      if ((i & 0x00ff) != 0) 
	output_asm_insn (\"xor	%s2,%s0\", operands);
      if ((i & 0xff00) != 0) 
	output_asm_insn (\"xor	%t2,%t0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"xor.w	%T2,%T0\";
  return \"xor	%s2,%s0\;xor	%t2,%t0\";
}"
  [(set_attr "length" "2,4")
   (set_attr "cc" "clobber,clobber")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      int i = INTVAL (operands[2]);

      /* The h8300h can't do byte-wise operations on the
	 upper 16bits of 32bit registers.  However, if
	 those bits aren't going to change, then we can
	 work on the low-order bits.  */
      if ((TARGET_H8300H || TARGET_H8300S)
	  && (i & 0xffff0000) != 0x00000000)
        return \"xor.l	%S2,%S0\";

      if ((i & 0x000000ff) != 0) 
	output_asm_insn (\"xor	%w2,%w0\", operands);
      if ((i & 0x0000ff00) != 0) 
	output_asm_insn (\"xor	%x2,%x0\", operands);
      if ((i & 0x00ff0000) != 0) 
	output_asm_insn (\"xor	%y2,%y0\", operands);
      if ((i & 0xff000000) != 0) 
	output_asm_insn (\"xor	%z2,%z0\", operands);
      return \"\";
    }
  if (TARGET_H8300H || TARGET_H8300S)
    return \"xor.l	%S2,%S0\";
  return \"xor	%w2,%w0\;xor	%x2,%x0\;xor	%y2,%y0\;xor	%z2,%z0\;\";
}"
  [(set_attr "length" "2,8")
   (set_attr "cc" "clobber,clobber")])

;; ----------------------------------------------------------------------
;; NEGATION INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
  ""
  "neg	%X0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_expand "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "
{
  if (TARGET_H8300)
    {
      emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
      DONE;
    }
}")

(define_expand "neghi2_h8300"
  [(set (match_dup 2)
	(not:HI (match_operand:HI 1 "register_operand" "r")))
   (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
   (set (match_operand:HI 0 "register_operand" "=r")
	(match_dup 2))]
  ""
  "{ operands[2] = gen_reg_rtx (HImode); }")

(define_insn "neghi2_h8300h"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
  "TARGET_H8300H || TARGET_H8300S"
  "neg	%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_expand "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
  ""
  "
{
  if (TARGET_H8300)
    {
      emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
      DONE;
    }
}")

(define_expand "negsi2_h8300"
  [(set (match_dup 2)
	(not:SI (match_operand:SI 1 "register_operand" "r")))
   (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(match_dup 2))]
  ""
  "{ operands[2] = gen_reg_rtx(SImode); }")

(define_insn "negsi2_h8300h"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
  "TARGET_H8300H || TARGET_H8300S"
  "neg	%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])