h8300.h

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/* Definitions of target machine for GNU compiler. 
   Hitachi H8/300 version generating coff 
   Copyright (C) 1992, 93-98, 1999 Free SoftwareFoundation, Inc.
   Contributed by Steve Chamberlain ([e-mail]),
   Jim Wilson ([e-mail]), and Doug Evans ([e-mail]).

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

/* Which cpu to compile for.
   We use int for CPU_TYPE to avoid lots of casts.  */
#if 0 /* defined in insn-attr.h, here for documentation */
enum attr_cpu { CPU_H8300, CPU_H8300H };
#endif
extern int cpu_type;

/* Various globals defined in h8300.c.  */

extern char *h8_push_op,*h8_pop_op,*h8_mov_op;
extern char **h8_reg_names;

/* Names to predefine in the preprocessor for this target machine.  */

#define CPP_PREDEFINES \
"-D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L"

#define CPP_SPEC \
  "%{!mh:%{!ms:-D__H8300__}} %{mh:-D__H8300H__} %{ms:-D__H8300S__} \
   %{!mh:%{!ms:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
   %{mh:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
   %{ms:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
   %{!mh:%{!ms:-Acpu(h8300) -Amachine(h8300)}} \
   %{mh:-Acpu(h8300h) -Amachine(h8300h)} \
   %{ms:-Acpu(h8300s) -Amachine(h8300s)} \
   %{!mint32:-D__INT_MAX__=32767} %{mint32:-D__INT_MAX__=2147483647}"

#define LINK_SPEC "%{mh:-m h8300h} %{ms:-m h8300s}"

#define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"

/* Print subsidiary information on the compiler version in use.  */

#define TARGET_VERSION fprintf (stderr, " (Hitachi H8/300)");

/* Run-time compilation parameters selecting different hardware subsets.  */

extern int target_flags;

/* Macros used in the machine description to test the flags.  */

/* Make int's 32 bits.  */
#define TARGET_INT32 (target_flags & 8)

/* Dump recorded insn lengths into the output file.  This helps debug the
   md file.  */
#define TARGET_ADDRESSES (target_flags & 64)

/* Pass the first few arguments in registers.  */
#define TARGET_QUICKCALL (target_flags & 128)

/* Pretend byte accesses are slow.  */
#define TARGET_SLOWBYTE (target_flags & 256)

/* Dump each assembler insn's rtl into the output file.
   This is for debugging the compiler only.  */
#define TARGET_RTL_DUMP	(target_flags & 2048)

/* Select between the h8/300 and h8/300h cpus.  */
#define TARGET_H8300	(! TARGET_H8300H && ! TARGET_H8300S)
#define TARGET_H8300H	(target_flags & 4096)
#define TARGET_H8300S	(target_flags & 1)

/* Align all values on the h8/300h the same way as the h8/300.  Specifically,
   32 bit and larger values are aligned on 16 bit boundaries.
   This is all the hardware requires, but the default is 32 bits for the 300h.
   ??? Now watch someone add hardware floating point requiring 32 bit
   alignment.  */
#define TARGET_ALIGN_300 (target_flags & 8192)

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES  \
  { {"s",		1,     "Generate H8/S code"},			\
    {"no-s",		-1,    "Do not generate H8/S code"},		\
    {"int32",		8,     "Make integers 32 bits wide"},		\
    {"addresses",	64,    NULL},					\
    {"quickcall",	128,   "Use registers for argument passing"},  	\
    {"no-quickcall",	-128,  "Do not use registers for argument passing"},\
    {"slowbyte",	256,   "Consider access to byte sized memory slow"},\
    {"relax",		1024,  "Enable linker relaxing"},		\
    {"rtl-dump",	2048,  NULL},					\
    {"h",		4096,  "Generate H8/300H code"},		\
    {"no-h",		-4096, "Do not generate H8/300H code"},		\
    {"align-300",	8192,  "Use H8/300 alignment rules"},		\
    { "", TARGET_DEFAULT, NULL}}

/* Do things that must be done once at start up.  */

#define OVERRIDE_OPTIONS \
do {				\
  h8300_init_once ();		\
} while (0)

/* Default target_flags if no switches specified.  */

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (128)	/* quickcall */
#endif

/* Show we can debug even without a frame pointer.  */
/* #define CAN_DEBUG_WITHOUT_FP */

/* Define this if addresses of constant functions
   shouldn't be put through pseudo regs where they can be cse'd.
   Desirable on machines where ordinary constants are expensive
   but a CALL with constant address is cheap. 

   Calls through a register are cheaper than calls to named
   functions; however, the register pressure this causes makes
   CSEing of function addresses generally a lose.  */
#define NO_FUNCTION_CSE 

/* Target machine storage layout */

/* Define to use software floating point emulator for REAL_ARITHMETIC and
   decimal <-> binary conversion. */
#define REAL_ARITHMETIC

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   This is not true on the H8/300.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on the H8/300.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is lowest
   numbered.  
   This is true on an H8/300 (actually we can make it up, but we choose to
   be consistent).  */ 
#define WORDS_BIG_ENDIAN 1

/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 32 : 16)
#define MAX_BITS_PER_WORD	32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MIN_UNITS_PER_WORD	2

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE (TARGET_H8300H || TARGET_H8300S ? 32 : 16)

#define SHORT_TYPE_SIZE 	16
#define INT_TYPE_SIZE 		(TARGET_INT32 ? 32 : 16)
#define LONG_TYPE_SIZE 		32
#define LONG_LONG_TYPE_SIZE	32
#define FLOAT_TYPE_SIZE 	32
#define DOUBLE_TYPE_SIZE 	32
#define LONG_DOUBLE_TYPE_SIZE 	DOUBLE_TYPE_SIZE

#define MAX_FIXED_MODE_SIZE 	32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Alignment of field after `int : 0' in a structure.  */
/* One can argue this should be 32 for -mint32, but since 32 bit ints only
   need 16 bit alignment, this is left as is so that -mint32 doesn't change
   structure layouts.  */
#define EMPTY_FIELD_BOUNDARY 16

/* A bitfield declared as `int' forces `int' alignment for the struct.  */
#define PCC_BITFIELD_TYPE_MATTERS  0

/* No data type wants to be aligned rounder than this.
   32 bit values are aligned as such on the 300h for speed.  */
#define BIGGEST_ALIGNMENT \
(((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16)

/* The stack goes in 16/32 bit lumps.  */
#define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32)

/* Define this if move instructions will actually fail to work
   when given unaligned data.  */
/* On the H8/300, longs can be aligned on halfword boundaries, but not
   byte boundaries.  */
#define STRICT_ALIGNMENT 1

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.  

   Reg 9 does not correspond to any hardware register, but instead
   appears in the RTL as an argument pointer prior to reload, and is
   eliminated during reloading in favor of either the stack or frame
   pointer.  */

#define FIRST_PSEUDO_REGISTER 10

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */

#define FIXED_REGISTERS \
  { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you
   like.  

   h8 destroys r0,r1,r2,r3.  */

#define CALL_USED_REGISTERS \
  { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1 }

#define REG_ALLOC_ORDER \
  { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9}

#define CONDITIONAL_REGISTER_USAGE	\
{					\
  if (!TARGET_H8300S)			\
    fixed_regs[8] = call_used_regs[8] = 1;\
}

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.

   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers. 

   We pretend the MAC register is 32bits -- we don't have any data
   types on the H8 series to handle more than 32bits.  */

#define HARD_REGNO_NREGS(REGNO, MODE)   \
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode
   MODE.

   H8/300: If an even reg, then anything goes. Otherwise the mode must be QI
           or HI.
   H8/300H: Anything goes.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE) \
 (TARGET_H8300 ? (((REGNO)&1)==0) || (MODE==HImode) || (MODE==QImode) \
   : REGNO == 8 ? MODE == SImode : 1)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)  ((MODE1) == (MODE2))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* H8/300 pc is not overloaded on a register.  */

/*#define PC_REGNUM 15*/

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 7

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 6

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM 9

/* Register in which static-chain is passed to a function.  */
#define STATIC_CHAIN_REGNUM 3

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */
   
enum reg_class {
  NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
};

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
{ "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS  			\
{      0,		/* No regs      */	\