mn10200.md

gcc编译工具没有什么特别

(define_insn "zero_extendhipsi2"
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(zero_extend:PSI
	 (match_operand:HI 1 "general_operand" "0,di,m")))]
  ""
  "@
  extxu %0
  mov %1,%0\;extxu %0
  mov %1,%0\;extxu %0"
  [(set_attr "cc" "none_0hit")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,d")
	(zero_extend:SI
	 (match_operand:HI 1 "general_operand" "0,dim")))]
  ""
  "@
  sub %H0,%H0
  mov %1,%L0\;sub %H0,%H0"
  [(set_attr "cc" "clobber,clobber")])

;; The last alternative is necessary because the second operand might
;; have been the frame pointer.  The frame pointer would get replaced
;; by (plus (stack_pointer) (const_int)).
;;
;; Reload would think that it only needed a PSImode register in
;; push_reload and at the start of allocate_reload_regs.  However,
;; at the end of allocate_reload_reg it would realize that the
;; reload register must also be valid for SImode, and if it was
;; not valid reload would abort.
(define_insn "zero_extendpsisi2"
  [(set (match_operand:SI 0 "register_operand" "=d,?d,?*d,?*d")
	(zero_extend:SI (match_operand:PSI 1 "extendpsi_operand"
						"m,?0,?*dai,Q")))]
  ""
  "@
  mov %L1,%L0\;movbu %H1,%H0
  jsr ___zero_extendpsisi2_%0
  mov %1,%L0\;jsr ___zero_extendpsisi2_%0
  mov a3,%L0\;add %Z1,%L0\;jsr ___zero_extendpsisi2_%0"
  [(set_attr "cc" "clobber")])

;;- sign extension instructions

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=d,d,d")
	(sign_extend:HI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"extxb %0\";
  else if (which_alternative == 1)
    return \"mov %1,%0\;extxb %0\";
  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
    return \"movbu %1,%0\;extxb %0\";
  else
    return \"movb %1,%0\";
}"
  [(set_attr "cc" "none_0hit")])

(define_insn "extendqipsi2"
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(sign_extend:PSI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"extxb %0\";
  else if (which_alternative == 1)
    return \"mov %1,%0\;extxb %0\";
  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
    return \"movbu %1,%0\;extxb %0\";
  else
    return \"movb %1,%0\";
}"
  [(set_attr "cc" "none_0hit")])

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
	(sign_extend:SI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
  else if (which_alternative == 1)
    return \"mov %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
    return \"movbu %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
  else
    return \"movb %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
}"
  [(set_attr "cc" "clobber")])

(define_insn "extendhipsi2"
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(sign_extend:PSI
	 (match_operand:HI 1 "general_operand" "0,di,m")))]
  ""
  "@
  extx %0
  mov %1,%0\;extx %0
  mov %1,%0"
  [(set_attr "cc" "none_0hit")])

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
	(sign_extend:SI
	 (match_operand:HI 1 "general_operand" "0,di,m")))]
  ""
  "@
  mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
  mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
  mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0"
  [(set_attr "cc" "clobber")])

;; The last alternative is necessary because the second operand might
;; have been the frame pointer.  The frame pointer would get replaced
;; by (plus (stack_pointer) (const_int)).
;;
;; Reload would think that it only needed a PSImode register in
;; push_reload and at the start of allocate_reload_regs.  However,
;; at the end of allocate_reload_reg it would realize that the
;; reload register must also be valid for SImode, and if it was
;; not valid reload would abort.
(define_insn "extendpsisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,?d,?*d,?*d")
	(sign_extend:SI (match_operand:PSI 1 "extendpsi_operand"
						"m,?0,?*dai,Q")))]
  ""
  "@
  mov %L1,%L0\;movb %H1,%H0
  jsr ___sign_extendpsisi2_%0
  mov %1,%L0\;jsr ___sign_extendpsisi2_%0
  mov a3,%L0\;add %Z1,%L0\;jsr ___sign_extendpsisi2_%0"
  [(set_attr "cc" "clobber")])

(define_insn "truncsipsi2"
  [(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da")
	(truncate:PSI (match_operand:SI 1 "general_operand" "m,?m,?*d,i")))]
   ""
   "@
   mov %1,%0
   movx %A1,%0
   jsr ___truncsipsi2_%1_%0
   mov %1,%0"
  [(set_attr "cc" "clobber")])


;; Combine should be simplifying this stuff, but isn't.
;;
(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
	(sign_extend:SI
	  (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m"))))]
  ""
  "@
  extxbu %L0\;sub %H0,%H0
  mov %1,%L0\;extxbu %L0\;sub %H0,%H0
  movbu %1,%L0\;sub %H0,%H0"
  [(set_attr "cc" "clobber")])

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
        (truncate:PSI
	  (sign_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"extxb %0\";
  else if (which_alternative == 1)
    return \"mov %1,%0\;extxb %0\";
  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
    return \"movbu %1,%0\;extxb %0\";
  else
    return \"movb %1,%0\";
}"
  [(set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(truncate:PSI
	  (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
  ""
  "@
  extx %0
  mov %1,%0\;extx %0
  mov %1,%0"
  [(set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(truncate:PSI
	  (sign_extend:SI
	    (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))))]
  ""
  "@
  extxbu %0
  mov %1,%0\;extxbu %0
  movbu %1,%0"
  [(set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(truncate:PSI
	  (zero_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
  ""
  "@
  extxu %0
  mov %1,%0\;extxu %0
  mov %1,%0\;extxu %0"
  [(set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
        (truncate:PSI
	  (zero_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
  ""
  "@
  extxbu %0
  mov %1,%0\;extxbu %0
  movbu %1,%0"
  [(set_attr "cc" "none_0hit")])

;; ----------------------------------------------------------------------
;; SHIFTS
;; ----------------------------------------------------------------------

;; If the shift count is small, we expand it into several single bit
;; shift insns.  Otherwise we expand into a generic shift insn which
;; handles larger shift counts, shift by variable amounts, etc.
(define_expand "ashlhi3"
  [(set (match_operand:HI 0 "general_operand" "")
	(ashift:HI (match_operand:HI 1 "general_operand" "")
		   (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* This is an experiment to see if exposing more of the underlying
     operations results in better code.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) <= 4)
    {
      int count = INTVAL (operands[2]);
      emit_move_insn (operands[0], operands[1]);
      while (count > 0)
	{
	  emit_insn (gen_rtx (SET, HImode, operands[0],
			      gen_rtx (ASHIFT, HImode,
				       operands[0], GEN_INT (1))));
	  count--;
	}
      DONE;
    }
  else
    {
      expand_a_shift (HImode, ASHIFT, operands);
      DONE;
    }
}")

;; ASHIFT one bit.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d")
	(ashift:HI (match_operand:HI 1 "general_operand" "0")
		   (const_int 1)))]
  ""
  "add %0,%0"
  [(set_attr "cc" "set_zn")])

(define_expand "lshrhi3"
  [(set (match_operand:HI 0 "general_operand" "")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* This is an experiment to see if exposing more of the underlying
     operations results in better code.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) <= 4)
    {
      int count = INTVAL (operands[2]);
      emit_move_insn (operands[0], operands[1]);
      while (count > 0)
	{
	  emit_insn (gen_rtx (SET, HImode, operands[0],
			      gen_rtx (LSHIFTRT, HImode,
				       operands[0], GEN_INT (1))));
	  count--;
	}
      DONE;
    }
  else
    {
      expand_a_shift (HImode, LSHIFTRT, operands);
      DONE;
    }
}")

;; LSHIFTRT one bit.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (const_int 1)))]
  ""
  "lsr %0"
  [(set_attr "cc" "set_znv")])

(define_expand "ashrhi3"
  [(set (match_operand:HI 0 "general_operand" "")
	(ashiftrt:HI (match_operand:HI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* This is an experiment to see if exposing more of the underlying
     operations results in better code.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) <= 4)
    {
      int count = INTVAL (operands[2]);
      emit_move_insn (operands[0], operands[1]);
      while (count > 0)
	{
	  emit_insn (gen_rtx (SET, HImode, operands[0],
			      gen_rtx (ASHIFTRT, HImode,
				       operands[0], GEN_INT (1))));
	  count--;
	}
      DONE;
    }
  else
    {
      expand_a_shift (HImode, ASHIFTRT, operands);
      DONE;
    }
}")

;; ASHIFTRT one bit.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d")
	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (const_int 1)))]
  ""
  "asr %0"
  [(set_attr "cc" "set_znv")])

;; And the general HImode shift pattern.  Handles both shift by constants
;; and shift by variable counts.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d,d")
	(match_operator:HI 3 "nshift_operator" 
			[ (match_operand:HI 1 "general_operand" "0,0")
			  (match_operand:HI 2 "general_operand" "KL,dan")]))
   (clobber (match_scratch:HI 4 "=X,&d"))]
  ""
  "* return emit_a_shift (insn, operands);"
  [(set_attr "cc" "clobber")])

;; We expect only ASHIFT with constant shift counts to be common for
;; PSImode, so we optimize just that case.  For all other cases we
;; extend the value to SImode and perform the shift in SImode.
(define_expand "ashlpsi3"
  [(set (match_operand:PSI 0 "general_operand" "")
	(ashift:PSI (match_operand:PSI 1 "general_operand" "")
		   (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* This is an experiment to see if exposing more of the underlying
     operations results in better code.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) <= 7)
    {
      int count = INTVAL (operands[2]);
      emit_move_insn (operands[0], operands[1]);
      while (count > 0)
	{
	  emit_insn (gen_rtx (SET, PSImode, operands[0],
			      gen_rtx (ASHIFT, PSImode,
				       operands[0], GEN_INT (1))));
	  count--;
	}
      DONE;
    }
  else
    {
      expand_a_shift (PSImode, ASHIFT, operands);
      DONE;
    }
}")

;; ASHIFT one bit.
(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d")
	(ashift:PSI (match_operand:PSI 1 "general_operand" "0")
		    (const_int 1)))]
  ""
  "add %0,%0"
  [(set_attr "cc" "set_zn")])

(define_expand "lshrpsi3"
  [(set (match_operand:PSI 0 "general_operand" "")
	(lshiftrt:PSI (match_operand:PSI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  rtx reg = gen_reg_rtx (SImode);

  emit_insn (gen_zero_extendpsisi2 (reg, operands[1]));
  reg = expand_binop (SImode, lshr_optab, reg,
		      operands[2], reg, 1, OPTAB_WIDEN);
  emit_insn (gen_truncsipsi2 (operands[0], reg));
  DONE;
}")

(define_expand "ashrpsi3"
  [(set (match_operand:PSI 0 "general_operand" "")
	(ashiftrt:PSI (match_operand:PSI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  rtx reg = gen_reg_rtx (SImode);

  emit_insn (gen_extendpsisi2 (reg, operands[1]));
  reg = expand_binop (SImode, ashr_optab, reg,
		      operands[2], reg, 0, OPTAB_WIDEN);
  emit_insn (gen_truncsipsi2 (operands[0], reg));
  DONE;
}")

(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashift:SI (match_operand:SI 1 "nonmemory_operand" "")
		   (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* For small shifts, just emit a series of single bit shifts inline.

     For other constant shift counts smaller than a word or non-constant
     shift counts we call out to a library call during RTL generation time;
     after RTL generation time we allow optabs.c to open code the operation.
     See comments in addsi3/subsi3 expanders.

     Otherwise we allow optabs.c to open code the operation.  */
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) <= 3))
    {
      int count = INTVAL (operands[2]);
      emit_move_insn (operands[0], operands[1]);
      while (count > 0)
	{
	  emit_insn (gen_rtx (SET, SImode, operands[0],
				   gen_rtx (ASHIFT, SImode,
					    operands[0], GEN_INT (1))));
	  count--;
	}
      DONE;
    }
  else if (rtx_equal_function_value_matters
	   && (GET_CODE (operands[2]) != CONST_INT
	       || INTVAL (operands[2]) <= 15))
    {
      rtx ret, insns;

      start_sequence ();
      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__ashlsi3\"),
				     NULL_RTX, 1, SImode, 2, operands[1],
				     SImode, operands[2], HImode);
      insns = get_insns ();
      end_sequence ();
      emit_libcall_block (insns, operands[0], ret,
			  gen_rtx (ASHIFT, SImode, operands[1], operands[2]));
      DONE;
    }
  else
    FAIL;
}")

;; ASHIFT one bit.
(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d")
	(ashift:SI (match_operand:SI 1 "general_operand" "0")
		     (const_int 1)))]
  ""
  "add %L0,%L0\;addc %H0,%H0"
  [(set_attr "cc" "clobber")])

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "")
		     (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  /* For small shifts, just emit a series of single bit shifts inline.

     For other constant shift counts smaller than a word or non-constant
     shift counts we call out to a library call during RTL generation time;
     after RTL generation time we allow optabs.c to open code the operation.
     See comments in addsi3/subsi3 expanders.