mn10200.md

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;; The not/and sequence won't work here.  It's not clear if we'll
;; ever need to provide an alternate sequence since this should
;; be used much less frequently than neghi2.
(define_insn "negpsi2"
  [(set (match_operand:PSI 0 "general_operand" "=&d")
        (neg:PSI (match_operand:PSI 1 "general_operand" "d")))]
  ""
  "sub %0,%0\;sub %1,%0"
  [(set_attr "cc" "set_zn")])

;; Using a magic libcall that accepts its arguments in any
;; data register pair has proven to be the most efficient
;; and most compact way to represent negsi2.
(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(neg:SI (match_operand:SI 1 "register_operand" "0")))]
  ""
  "jsr ___negsi2_%0"
  [(set_attr "cc" "clobber")])
 
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------
;;
;; The mn10200 has HIxHI->SI widening multiply, but we get _severe_
;; code density regressions if we enable such a pattern.

(define_insn "mulhi3"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(mult:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "d")))]
  ""
  "mul %2,%0"
  [(set_attr "cc" "set_zn")])

(define_insn "udivmodhi4"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(udiv:HI (match_operand:HI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "d")))
   (set (match_operand:HI 3 "general_operand" "=&d")
	(umod:HI (match_dup 1) (match_dup 2)))]
  ""
  "*
{
  if (zero_dreg)
    output_asm_insn (\"mov %0,mdr\", &zero_dreg);
  else
    output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
    
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divu %2,%0\";
  else
    return \"divu %2,%0\;mov mdr,%3\";
}"
  [(set_attr "cc" "set_zn")])


;; ----------------------------------------------------------------------
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "andhi3"
  [(set (match_operand:HI 0 "general_operand" "=d,d")
	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "M,di")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
    return \"extxbu %0\";
  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fff)
    return \"add %0,%0\;lsr %0\";
  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffe)
    return \"lsr %0\;add %0,%0\";
  return \"and %2,%0\";
}"
  [(set_attr "cc" "none_0hit,set_znv")])

;; This expander + pattern exist only to allow trampolines to be aligned
;; in the stack.
(define_expand "andpsi3"
  [(set (match_operand:PSI 0 "general_operand" "")
	(and:PSI (match_operand:PSI 1 "general_operand" "")
		(match_operand:PSI 2 "const_int_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT
      || (INTVAL (operands[2]) & 0xff0000) != 0xff0000)
    FAIL;
}")

(define_insn ""
  [(set (match_operand:PSI 0 "general_operand" "=d")
	(and:PSI (match_operand:PSI 1 "general_operand" "%0")
		(match_operand:PSI 2 "const_int_operand" "i")))]
  "GET_CODE (operands[2]) == CONST_INT
   && (INTVAL (operands[2]) & 0xff0000) == 0xff0000"
  "and %2,%0"
  [(set_attr "cc" "clobber")])

;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(ior:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "di")))]
  ""
  "or %2,%0"
  [(set_attr "cc" "set_znv")])

;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(xor:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "di")))]
  ""
  "xor %2,%0"
  [(set_attr "cc" "set_znv")])

;; ----------------------------------------------------------------------
;; NOT INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(not:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "not %0"
  [(set_attr "cc" "set_znv")])


;; -----------------------------------------------------------------
;; BIT INSTRUCTIONS
;; -----------------------------------------------------------------

;; These clears a constant set of bits in memory or in a register.
;; We must support register destinations to make reload happy.
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "+R,d")
	(subreg:QI
	  (and:HI (subreg:HI (match_dup 0) 0)
		  (match_operand 1 "const_int_operand" "")) 0))
   (clobber (match_scratch:HI 2 "=&d,X"))]
  ""
  "@
  mov %N1,%2\;bclr %2,%0
  and %1,%0"
  [(set_attr "cc" "clobber")])

;; This clears a variable set of bits in memory or in a register.
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "+R,d")
	(subreg:QI
	  (and:HI (subreg:HI (match_dup 0) 0)
		  (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
   (clobber (match_scratch:HI 2 "=X,&d"))]
  ""
  "@
  bclr %1,%0
  mov %1,%2\;not %2\;and %2,%0"
  [(set_attr "cc" "clobber")])

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "+R,d")
	(subreg:QI
	  (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
		  (subreg:HI (match_dup 0) 0)) 0))
   (clobber (match_scratch:HI 2 "=X,&d"))]
  ""
  "@
  bclr %1,%0
  mov %1,%2\;not %2\;and %2,%0"
  [(set_attr "cc" "clobber")])

;; These set bits in memory.
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "+R,d")
	(subreg:QI
	  (ior:HI (subreg:HI (match_dup 0) 0)
		  (match_operand:HI 1 "general_operand" "d,d")) 0))]
  ""
  "@
  bset %1,%0
  or %1,%0"
  [(set_attr "cc" "clobber")])

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "+R,d")
	(subreg:QI
	  (ior:HI (match_operand:HI 1 "general_operand" "d,d")
		  (subreg:HI (match_dup 0) 0)) 0))]
  ""
  "@
  bset %1,%0
  or %1,%0"
  [(set_attr "cc" "clobber")])

;; Not any shorter/faster than using cmp, but it might save a
;; register if the result of the AND isn't ever used.

(define_insn ""
  [(set (cc0)
     (zero_extract:HI (match_operand:HI 0 "general_operand" "d")
		      (match_operand 1 "const_int_operand" "")
		      (match_operand 2 "const_int_operand" "")))]
  ""
  "*
{
  int len = INTVAL (operands[1]);
  int bit = INTVAL (operands[2]);
  int mask = 0;
  rtx xoperands[2];

  while (len > 0)
    {
      mask |= (1 << bit);
      bit++;
      len--;
    }

  xoperands[0] = operands[0];
  xoperands[1] = GEN_INT (mask);
  output_asm_insn (\"btst %1,%0\", xoperands);
  return \"\";
}"
  [(set_attr "cc" "clobber")])

(define_insn ""
  [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "d")
		      (match_operand:HI 1 "const_int_operand" "i")))]
  ""
  "btst %1,%0"
  [(set_attr "cc" "clobber")])


;; ----------------------------------------------------------------------
;; JUMP INSTRUCTIONS
;; ----------------------------------------------------------------------

;; Conditional jump instructions

(define_expand "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "")

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator"
				      [(cc0) (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
      && (GET_CODE (operands[1]) == GT
          || GET_CODE (operands[1]) == GE
          || GET_CODE (operands[1]) == LE
          || GET_CODE (operands[1]) == LT))
    return 0;

  if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
    return \"b%b1x %0\";
  else
    return \"b%b1 %0\";
}"
 [(set_attr "cc" "none")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 1 "comparison_operator"
				      [(cc0) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
{
  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
      && (GET_CODE (operands[1]) == GT
          || GET_CODE (operands[1]) == GE
          || GET_CODE (operands[1]) == LE
          || GET_CODE (operands[1]) == LT))
    return 0;

  if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
    return \"b%B1x %0\";
  else
    return \"b%B1 %0\";
}"
 [(set_attr "cc" "none")])

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jmp %l0"
 [(set_attr "cc" "none")])

(define_insn "indirect_jump"
  [(set (pc) (match_operand:PSI 0 "general_operand" "a"))]
  ""
  "jmp (%0)"
  [(set_attr "cc" "none")])

(define_insn "tablejump"
  [(set (pc) (match_operand:PSI 0 "general_operand" "a"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp  (%0)"
  [(set_attr "cc" "none")])

;; Call subroutine with no return value.

(define_expand "call"
  [(call (match_operand:QI 0 "general_operand" "")
	 (match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  if (! call_address_operand (XEXP (operands[0], 0)))
    XEXP (operands[0], 0) = force_reg (PSImode, XEXP (operands[0], 0));
  emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
  DONE;
}")

(define_insn "call_internal"
  [(call (mem:QI (match_operand:PSI 0 "call_address_operand" "aS"))
	 (match_operand:HI 1 "general_operand" "g"))]
  ""
  "jsr %C0"
  [(set_attr "cc" "clobber")])

;; Call subroutine, returning value in operand 0
;; (which must be a hard register).

(define_expand "call_value"
  [(set (match_operand 0 "" "")
	(call (match_operand:QI 1 "general_operand" "")
	      (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  if (! call_address_operand (XEXP (operands[1], 0)))
    XEXP (operands[1], 0) = force_reg (PSImode, XEXP (operands[1], 0));
  emit_call_insn (gen_call_value_internal (operands[0],
					   XEXP (operands[1], 0),
					   operands[2]));
  DONE;
}")

(define_insn "call_value_internal"
  [(set (match_operand 0 "" "=da")
	(call (mem:QI (match_operand:PSI 1 "call_address_operand" "aS"))
	      (match_operand:HI 2 "general_operand" "g")))]
  ""
  "jsr %C1"
  [(set_attr "cc" "clobber")])

(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
                    (const_int 0))
              (match_operand 1 "" "")
              (match_operand 2 "" "")])]
  ""
  "
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }
  DONE;
}")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop"
  [(set_attr "cc" "none")])

;; ----------------------------------------------------------------------
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=d,d,d")
	(zero_extend:HI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "@
  extxbu %0
  mov %1,%0\;extxbu %0
  movbu %1,%0"
  [(set_attr "cc" "none_0hit")])

(define_insn "zero_extendqipsi2"
  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
	(zero_extend:PSI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "@
  extxbu %0
  mov %1,%0\;extxbu %0
  movbu %1,%0"
  [(set_attr "cc" "none_0hit")])

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
	(zero_extend:SI
	 (match_operand:QI 1 "general_operand" "0,di,m")))]
  ""
  "@
  extxbu %L0\;sub %H0,%H0
  mov %1,%L0\;extxbu %L0\;sub %H0,%H0
  movbu %1,%L0\;sub %H0,%H0"
  [(set_attr "cc" "clobber")])