convex.md

gcc编译工具没有什么特别

		 (match_operand:HI 1 "nonmemory_operand" "di,ai")))]
  ""
  "* return output_cmp (operands[0], operands[1], 'h');")

; cmpqi is intentionally omitted.
;
; gcc will sign-extend or zero-extend the operands to the next
; wider mode, HImode.
;
; For reg .cmp. constant, we just go with the halfword immediate
; instruction.  Perhaps the widening insn can be cse'd or combined away.
; If not, we're still as good as loading a byte constant into a register
; to do a reg-reg byte compare.
;
; The following patterns pick up cases that can use reg .cmp. reg after all.

(define_insn ""
  [(set (cc0)
	(compare
	 (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
	 (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))]
  ""
  "* return output_cmp (operands[0], operands[1], 'b');")

(define_insn ""
  [(set (cc0)
	(compare
	 (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0)
		    (const_int 8))
	 (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0)
		    (const_int 8))))]
  ""
  "* return output_cmp (operands[0], operands[1], 'b');")

(define_insn ""
  [(set (cc0)
	(compare (match_operand:QI 0 "register_operand" "d")
		 (match_operand:QI 1 "register_operand" "d")))]
  ""
  "* return output_cmp (operands[0], operands[1], 'b');")

(define_insn ""
  [(set (cc0) (match_operand:QI 0 "register_operand" "d"))
   (clobber (match_scratch:QI 1 "=d"))]
  "next_insn_tests_no_inequality (insn)"
  "* return output_cmp (operands[0], operands[1], 'B');")

(define_insn ""
  [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0))
   (clobber (match_scratch:QI 1 "=d"))]
  "next_insn_tests_no_inequality (insn)"
  "* return output_cmp (operands[0], operands[1], 'B');")

(define_insn ""
  [(set (cc0)
	(zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0)))
   (clobber (match_scratch:QI 1 "=d"))]
  "next_insn_tests_no_inequality (insn)"
  "* return output_cmp (operands[0], operands[1], 'B');")

(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "d")
		 (match_operand:DF 1 "register_operand" "d")))]
  ""
  "* return output_cmp (operands[0], operands[1], 'd');")

(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "register_operand" "d")
		 (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))]
  ""
  "* return output_cmp (operands[0], operands[1], 's');")

;; decrement-and-set-cc0 insns.
;;
;; The most important case where we can use the carry bit from an
;; arithmetic insn to eliminate a redundant compare is the decrement in
;; constructs like while (n--) and while (--n >= 0).  
;;
;; We do it with combine patterns instead of NOTICE_UPDATE_CC because
;; the decrement needs to be kept at the end of the block during scheduling.
;; 
;; These patterns must have memory alternatives because reload refuses
;; to do output reloads for an insn that sets cc0 (since it does not
;; want to clobber cc0 with its moves).  Convex moves do not clobber
;; cc0, but there is no evident way to get reload to know that.

(define_insn ""
  [(set (cc0)
	(match_operand:SI 0 "register_operand" "+r,*m"))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))]
  "next_insn_tests_no_inequality (insn)"
  "*
{
  if (which_alternative == 0)
    {
      output_cmp (operands[0], constm1_rtx, 'W');
      return \"add.w #-1,%0\";
    }
  else
    {
      output_cmp (gen_rtx (REG, SImode, 7), constm1_rtx, 'W');
      return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
    }
}")
     
(define_insn ""
  [(set (cc0)
	(plus:SI (match_operand:SI 0 "register_operand" "+r,*m")
		 (const_int -1)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))]
  "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
  "*
{
  if (which_alternative == 0)
    {
      output_cmp (operands[0], const0_rtx, 'W');
      return \"add.w #-1,%0\";
    }
  else
    {
      output_cmp (gen_rtx (REG, SImode, 7), const0_rtx, 'W');
      return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
    }
}")

(define_insn ""
  [(set (cc0)
	(match_operand:HI 0 "register_operand" "+r,*m"))
   (set (match_dup 0)
	(plus:HI (match_dup 0)
		 (const_int -1)))]
  "next_insn_tests_no_inequality (insn)"
  "*
{
  if (which_alternative == 0)
    {
      output_cmp (operands[0], constm1_rtx, 'H');
      return \"add.h #-1,%0\";
    }
  else
    {
      output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'H');
      return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
    }
}")
     
(define_insn ""
  [(set (cc0)
	(plus:HI (match_operand:HI 0 "register_operand" "+r,*m")
		 (const_int -1)))
   (set (match_dup 0)
	(plus:HI (match_dup 0)
		 (const_int -1)))]
  "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
  "*
{
  if (which_alternative == 0)
    {
      output_cmp (operands[0], const0_rtx, 'H');
      return \"add.h #-1,%0\";
    }
  else
    {
      output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'H');
      return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
    }
}")

;;- Jumps

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jbr %l0")

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"eq\", 't'); ")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"eq\", 'f'); ")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"le\", 'f'); ")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"leu\", 'f'); ")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"lt\", 't'); ")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"ltu\", 't'); ")

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"lt\", 'f'); ")

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"ltu\", 'f'); ")

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"le\", 't'); ")

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return output_condjump (operands[0], \"leu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"eq\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"eq\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"le\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"leu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"lt\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"ltu\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"lt\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"ltu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"le\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return output_condjump (operands[0], \"leu\", 'f'); ")

;;- Calls

(define_expand "call_pop"
  [(parallel [(call (match_operand:QI 0 "memory_operand" "m")
		    (match_operand:SI 1 "const_int_operand" "i"))
	      (match_operand:SI 2 "const_int_operand" "i")
	      (match_operand:SI 3 "const_int_operand" "i")
	      (reg:SI 8)])]
  ""
  "")

(define_insn ""
  [(call (match_operand:QI 0 "memory_operand" "m")
	 (match_operand:SI 1 "const_int_operand" "i"))
   (match_operand:SI 2 "const_int_operand" "i")
   (match_operand:SI 3 "const_int_operand" "i")
   (match_operand:SI 4 "" "")]
  ""
  "* return output_call (insn, &operands[0]);")

(define_expand "call_value_pop"
  [(parallel [(set (match_operand 0 "" "=g")
		   (call (match_operand:QI 1 "memory_operand" "m")
			 (match_operand:SI 2 "const_int_operand" "i")))
	      (match_operand:SI 3 "const_int_operand" "i")
	      (match_operand:SI 4 "const_int_operand" "i")
	      (reg:SI 8)])]
  ""
  "")

(define_insn ""
  [(set (match_operand 0 "" "=g")
	(call (match_operand:QI 1 "memory_operand" "m")
	      (match_operand:SI 2 "const_int_operand" "i")))
   (match_operand:SI 3 "const_int_operand" "i")
   (match_operand:SI 4 "const_int_operand" "i")
   (match_operand:SI 5 "" "")]
  ""
  "* return output_call (insn, &operands[1]); ")

;; Call subroutine returning any type.

(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
                  (const_int 0))
            (match_operand 1 "" "")
            (match_operand 2 "" "")])]
  ""
  "
{
  int i;

  emit_call_insn (gen_call_pop (operands[0], const0_rtx,
				const0_rtx, const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());

  DONE;
}")

;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory.  This blocks insns from being moved across this point.

(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] 0)]
  ""
  "")

(define_expand "return"
  [(return)]
  ""
  " replace_arg_pushes (); ")

(define_insn ""
  [(return)]
  ""
  "rtn")

(define_expand "prologue"
  [(const_int 0)]
  ""
  "
{
  emit_ap_optimizations ();
  DONE; 
}")

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp %a0")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
  ""
  "jmp %a0")