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gcc编译工具没有什么特别

(define_insn "xordi3"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(xor:DI (match_operand:DI 1 "register_operand" "%0")
		(match_operand:DI 2 "register_operand" "d")))]
  ""
  "xor %2,%0")

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
  ""
  "xor %2,%0")

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(xor:HI (match_operand:HI 1 "register_operand" "%0,0")
		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]
  ""
  "xor %2,%0")

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "=d,a")
	(xor:QI (match_operand:QI 1 "register_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]
  ""
  "xor %2,%0")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(neg:DF (match_operand:DF 1 "register_operand" "d")))]
  ""
  "neg.d %1,%0"
  [(set_attr "type" "addd")])

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(neg:SF (match_operand:SF 1 "register_operand" "d")))]
  ""
  "neg.s %1,%0"
  [(set_attr "type" "adds")])

(define_insn "negdi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
  ""
  "neg.l %1,%0")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "neg.w %1,%0")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
  ""
  "neg.h %1,%0")

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=d")
	(neg:QI (match_operand:QI 1 "register_operand" "d")))]
  ""
  "neg.b %1,%0")

(define_insn "one_cmpldi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(not:DI (match_operand:DI 1 "register_operand" "d")))]
  ""
  "not %1,%0")

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(not:SI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "not %1,%0")

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(not:HI (match_operand:HI 1 "register_operand" "d,a")))]
  ""
  "not %1,%0")

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "register_operand" "=d,a")
	(not:QI (match_operand:QI 1 "register_operand" "d,a")))]
  ""
  "not %1,%0")

;;- Shifts
;;
;; The extreme profusion of patterns here is due to the different-speed
;; shifts on different machines, and the C1's lack of word shift S-register
;; instructions.

;; SImode

;; Arithmetic left 1, 1 cycle on all machines via add

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "0")
		   (const_int 1)))]
  ""
  "add.w %0,%0")

;; C34 general shift is 1 cycle

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
  "TARGET_C34"
  "@
   shf.w %2,%0
   shf %2,%0"
  [(set_attr "type" "shfw,shfw")])

;; else shift left 0..7 is 1 cycle if we use an A register

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a,?d")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
  "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
  "@
   shf %2,%0
   shf %2,%0"
  [(set_attr "type" "alu,shfl")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a,?d")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
  "INTVAL (operands[2]) < (unsigned) 8"
  "@
   shf %2,%0
   shf.w %2,%0"
  [(set_attr "type" "alu,shfw")])

;; else general left shift

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
  "TARGET_C1"
  "@
   shf %2,%0
   shf %2,%0"
  [(set_attr "type" "shfl,shfw")])

;; but C2 left shift by a constant is faster via multiply

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "0")
		   (match_operand:SI 2 "const_int_operand" "i")))]
  "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
  "mul.w %z2,%0"
  [(set_attr "type" "mulw")])

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
  ""
  "@
   shf.w %2,%0
   shf %2,%0"
  [(set_attr "type" "shfw,shfw")])

;; Logical right, general
;; The hardware wants the negative of the shift count

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
  ""
  "operands[2] = negate_rtx (SImode, operands[2]);")

;; C1 lacks word shift S reg

(define_insn ""
  [(set
    (match_operand:SI 0 "register_operand" "=a,?d")
    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
		 (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))]
  "TARGET_C1"
  "@
   shf %2,%0
   ld.u #0,%0\;shf %2,%0"
  [(set_attr "type" "shfw,shfl")])

;; general case

(define_insn ""
  [(set
    (match_operand:SI 0 "register_operand" "=d,a")
    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
		 (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
  ""
  "@
   shf.w %2,%0
   shf %2,%0"
  [(set_attr "type" "shfw,shfw")])

;; Patterns without neg produced by constant folding

(define_insn ""
  [(set
    (match_operand:SI 0 "register_operand" "=a,?d")
    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
		 (match_operand:SI 2 "immediate_operand" "i,i")))]
  "TARGET_C1"
  "@
   shf #%n2,%0
   ld.u #0,%0\;shf #%n2,%0"
  [(set_attr "type" "shfw,shfl")])

(define_insn ""
  [(set
    (match_operand:SI 0 "register_operand" "=d,a")
    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
		 (match_operand:SI 2 "immediate_operand" "i,i")))]
  ""
  "@
   shf.w #%n2,%0
   shf #%n2,%0"
  [(set_attr "type" "shfw,shfw")])

;; Arithmetic right, general
;; Sign-extend to 64 bits, then shift that.  Works for 0..32.

(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
  ""
  "operands[2] = negate_rtx (SImode, operands[2]);")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,&d")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
		     (neg:SI
		      (match_operand:SI 2 "nonmemory_operand" "di,di"))))]
  ""
  "cvtw.l %1,%0\;shf %2,%0"
  [(set_attr "type" "shfl,shfl")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
		     (match_operand:SI 2 "immediate_operand" "i")))]
  ""
  "cvtw.l %1,%0\;shf #%n2,%0"
  [(set_attr "type" "shfl")])

;; DImode
;; Arithmetic left, 1-cycle

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(ashift:DI (match_operand:DI 1 "register_operand" "0")
		   (const_int 1)))]
  ""
  "add.l %0,%0")

;; Arithmetic left, general

(define_insn "ashldi3"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(ashift:DI (match_operand:DI 1 "register_operand" "0")
		   (match_operand:SI 2 "nonmemory_operand" "di")))]
  ""
  "shf %2,%0"
  [(set_attr "type" "shfl")])

;; Can omit zero- or sign-extend if shift is 32 or more.

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
		   (match_operand:SI 2 "const_int_operand" "i")))]
  "INTVAL (operands[2]) >= 32"
  "shf %2,%0"
  [(set_attr "type" "shfl")])

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
		   (match_operand:SI 2 "const_int_operand" "i")))]
  "INTVAL (operands[2]) >= 32"
  "shf %2,%0"
  [(set_attr "type" "shfl")])

;; Logical right, general

(define_expand "lshrdi3"
  [(set (match_operand:DI 0 "register_operand" "")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
  ""
  "operands[2] = negate_rtx (SImode, operands[2]);")

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
  ""
  "shf %2,%0"
  [(set_attr "type" "shfl")])

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
		     (match_operand:SI 2 "immediate_operand" "i")))]
  ""
  "shf #%n2,%0"
  [(set_attr "type" "shfl")])

;; Arithmetic right, general
;; Use
;;     ((a >> b) ^ signbit) - signbit
;; where signbit is (1 << 63) >> b
;; Works for 0..63.  Does not work for 64; unfortunate but valid.

(define_expand "ashrdi3"
  [(set (match_operand:DI 0 "register_operand" "")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))
   (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2))))
   (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3)))
   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
  ""
  "
{
  if (GET_CODE (operands[2]) == CONST_INT)
    switch (INTVAL (operands[2]))
      {
      case 32:
	emit_insn (gen_ashrdi3_32 (operands[0], operands[1]));
	DONE;
      }

  operands[2] = negate_rtx (SImode, operands[2]);
  operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
}")

;; Arithmetic right 32, a common case that can save a couple of insns.

(define_expand "ashrdi3_32"
  [(set (match_operand:DI 0 "register_operand" "")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
		     (const_int 32)))
   (set (match_dup 0)
	(sign_extend:DI (subreg:SI (match_dup 0) 0)))]
  ""
  "")

;; __builtin instructions

(define_insn "sqrtdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
  "! TARGET_C1 && flag_fast_math"
  "sqrt.d %0"
  [(set_attr "type" "divd")])

(define_insn "sqrtsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
  "! TARGET_C1 && flag_fast_math"
  "sqrt.s %0"
  [(set_attr "type" "divs")])

(define_insn "sindf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
  "! TARGET_C1 && flag_fast_math"
  "sin.d %0")

(define_insn "sinsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
  "! TARGET_C1 && flag_fast_math"
  "sin.s %0")

(define_insn "cosdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
  "! TARGET_C1 && flag_fast_math"
  "cos.d %0")

(define_insn "cossf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
  "! TARGET_C1 && flag_fast_math"
  "cos.s %0")

(define_insn "ftruncdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(fix:DF (match_operand:DF 1 "register_operand" "d")))]
  "! TARGET_C1"
  "frint.d %1,%0"
  [(set_attr "type" "cvtd")])

(define_insn "ftruncsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(fix:SF (match_operand:SF 1 "register_operand" "d")))]
  "! TARGET_C1"
  "frint.s %1,%0"
  [(set_attr "type" "cvts")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d")
	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
		  (const_int 1)))]
  ""
  "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:")

(define_expand "ffssi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
		  (const_int 1)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int 1)))]
  ""
  "")

(define_insn "abssf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
  ""
  "and #0x7fffffff,%0")

(define_expand "absdf2"
  [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
	(and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
		(match_dup 2)))]
  ""
  "operands[2] = force_reg (DImode,
                            immed_double_const (-1, 0x7fffffff, DImode));")

;;- Compares

(define_insn "cmpdi"
  [(set (cc0)
	(compare (match_operand:DI 0 "register_operand" "d")
		 (match_operand:DI 1 "register_operand" "d")))]
  ""
  "* return output_cmp (operands[0], operands[1], 'l');")

(define_insn ""
  [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
   (clobber (match_scratch:DI 1 "=d"))]
  "next_insn_tests_no_inequality (insn)"
  "* return output_cmp (operands[0], operands[1], 'L');")

(define_insn "cmpsi"
  [(set (cc0)
	(compare (match_operand:SI 0 "register_operand" "d,a")
		 (match_operand:SI 1 "nonmemory_operand" "di,ai")))]
  ""
  "* return output_cmp (operands[0], operands[1], 'w');")

(define_insn "cmphi"
  [(set (cc0)
	(compare (match_operand:HI 0 "register_operand" "d,a")