convex.md

gcc编译工具没有什么特别

;;- Machine description for GNU compiler, Convex Version
;;  Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc.

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;; Attribute specifications

; Target CPU
(define_attr "cpu" "c1,c32,c34,c38"
  (const (symbol_ref "(enum attr_cpu) target_cpu")))

;; Instruction classification

(define_attr "type"
  "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd"
  (const_string "alu"))

;; Instruction times

(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0)

(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0)

(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0)
(define_function_unit "mem" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0)

(define_function_unit "add" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2)
(define_function_unit "add" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1)
(define_function_unit "add" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2)
(define_function_unit "add" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1)

(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2)

(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3)
(define_function_unit "mul" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3)

(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10)

(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18)

(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9)

(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16)
(define_function_unit "div" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16)

(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1)

(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4)
(define_function_unit "misc" 1 0
  (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1)

(define_function_unit "mystery_latch" 1 1
  (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2)

;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c1")
;       (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2)
;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c1")
;       (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1)
;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c32")
;       (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2)
;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c32")
;       (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1)
;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c34")
;       (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2)
;(define_function_unit "ip" 1 1
;  (and (eq_attr "cpu" "c34")
;       (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1)

;; Make the first thing a real insn in case of genattrtab bug

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")

;; Moves

(define_expand "movdf"
  [(set (match_operand:DF 0 "general_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (DFmode, operands[1]);")

(define_insn ""
  [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m")
	(match_operand:DF 1 "general_operand"  "d,Q,m,G,H,d,d"))]
  "register_operand (operands[0], DFmode)
   || register_operand (operands[1], DFmode)"
  "@
   mov %1,%0
   ldb.d %1,%0
   ld.d %1,%0
   ld.d %u1,%0
   ld.l %v1,%0
   psh.l %1
   st.d %1,%0"
  [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])

;; This is here so we can load any result of RTL constant folding
;; but do not use it on constants that can be loaded from memory.
;; It is never better and can be worse.

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=d")
	(match_operand:DF 1 "const_double_operand" "F"))]
  "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
  "ld.u %u1,%0\;ld.w %v1,%0"
  [(set_attr "type" "xalu")])

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (SFmode, operands[1]);")

(define_insn ""
  [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m")
	(match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))]
  "register_operand (operands[0], SFmode)
   || register_operand (operands[1], SFmode)"
  "@
   mov.s %1,%0
   ldb.s %1,%0
   ld.s %1,%0
   ld.s %1,%0
   psh.w %1
   st.s %1,%0"
  [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")])

(define_expand "movdi"
  [(set (match_operand:DI 0 "general_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (DImode, operands[1]);")

(define_insn ""
  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m")
	(match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))]
  "register_operand (operands[0], DImode)
   || register_operand (operands[1], DImode)"
  "@
   mov %1,%0
   ldb.l %1,%0
   ld.l %1,%0
   ld.d %u1,%0
   ld.l %1,%0
   psh.l %1
   st.l %1,%0"
  [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])

;; This is here so we can load any result of RTL constant folding
;; but do not use it on constants that can be loaded from memory.
;; It is never better and can be worse.

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=d")
	(match_operand:DI 1 "const_double_operand" "F"))]
  "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
  "ld.u %u1,%0\;ld.w %v1,%0"
  [(set_attr "type" "xalu")])

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (SImode, operands[1]);")

(define_insn ""
  [(set (match_operand:SI 0 "push_operand" "=<,<")
	(match_operand:SI 1 "nonmemory_operand" "Ad,i"))]
  ""
  "@
   psh.w %1
   pshea %a1")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")
	(match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
  "register_operand (operands[0], SImode)
   || register_operand (operands[1], SImode)"
  "@
   mov.w %1,%0
   mov %1,%0
   ldb.w %1,%0
   ld.w %1,%0
   ld.w %1,%0
   st.w %1,%0"
  [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])

(define_expand "movstrictsi"
  [(set (strict_low_part (match_operand:SI 0 "general_operand" ""))
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (SImode, operands[1]);")

(define_insn ""
  [(set (strict_low_part (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m"))
	(match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
  "register_operand (operands[0], SImode)
   || register_operand (operands[1], SImode)"
  "@
   mov.w %1,%0
   mov %1,%0
   ldb.w %1,%0
   ld.w %1,%0
   ld.w %1,%0
   st.w %1,%0"
  [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (HImode, operands[1]);")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m")
	(match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
  "register_operand (operands[0], HImode)
   || register_operand (operands[1], HImode)"
  "@
   mov.w %1,%0
   mov %1,%0
   ldb.h %1,%0
   ld.h %1,%0
   ld.w %1,%0
   psh.w %1
   st.h %1,%0"
  [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (QImode, operands[1]);")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m")
	(match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
  "register_operand (operands[0], QImode)
   || register_operand (operands[1], QImode)"
  "@
   mov.w %1,%0
   mov %1,%0
   ldb.b %1,%0
   ld.b %1,%0
   ld.w %1,%0
   psh.w %1
   st.b %1,%0"
  [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])

;; Expand block moves manually to get code that pipelines the loads.

(define_expand "movstrsi"
  [(set (match_operand:BLK 0 "memory_operand" "=m")
	(match_operand:BLK 1 "memory_operand" "m"))
   (use (match_operand:SI 2 "const_int_operand" "i"))
   (use (match_operand:SI 3 "const_int_operand" "i"))]
  ""
  " expand_movstr (operands); DONE; ")

;; Extension and truncation insns.
;; Those for integer source operand
;; are ordered widest source type first.

(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "register_operand" "=d,a")
	(truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "cvtw.b %1,%0")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
  ""
  "cvtw.h %1,%0")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "")

(define_insn "truncdisi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(truncate:SI (match_operand:DI 1 "register_operand" "d")))]
  ""
  "cvtl.w %1,%0")

(define_insn "extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
  ""
  "cvtw.l %1,%0")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
  ""
  "cvth.w %1,%0")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=d,a")
	(sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
  ""
  "cvtb.w %1,%0")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=d,a")
	(sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
  ""
  "cvtb.w %1,%0")

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
  ""
  "cvts.d %1,%0"
  [(set_attr "type" "cvts")])

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
  ""
  "cvtd.s %1,%0"
  [(set_attr "type" "cvtd")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "and #0xffff,%0")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "and #0xff,%0")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "and #0xff,%0")

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
  ""
  "ld.u #0,%0")

;; Fix-to-float conversion insns.
;; Note that the ones that start with SImode come first.
;; That is so that an operand that is a CONST_INT
;; (and therefore lacks a specific machine mode).
;; will be recognized as SImode (which is always valid)
;; rather than as QImode or HImode.

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(float:SF (match_operand:SI 1 "register_operand" "d")))]
  ""
  "cvtw.s %1,%0"