arm.h

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{                         				\
  {"apcs",			ARM_FLAG_APCS_FRAME, "" }, \
  {"apcs-frame",		ARM_FLAG_APCS_FRAME, 	\
     "Generate APCS conformant stack frames" },		\
  {"no-apcs-frame",	       -ARM_FLAG_APCS_FRAME, "" }, \
  {"poke-function-name",	ARM_FLAG_POKE, 		\
     "Store function names in object code" },		\
  {"no-poke-function-name",    -ARM_FLAG_POKE, "" },	\
  {"fpe",			ARM_FLAG_FPE,  "" },	\
  {"apcs-32",			ARM_FLAG_APCS_32, 	\
     "Use the 32bit version of the APCS" },		\
  {"apcs-26",		       -ARM_FLAG_APCS_32, 	\
     "Use the 26bit version of the APCS" },		\
  {"apcs-stack-check",		ARM_FLAG_APCS_STACK, "" }, \
  {"no-apcs-stack-check",      -ARM_FLAG_APCS_STACK, "" }, \
  {"apcs-float",		ARM_FLAG_APCS_FLOAT, 	\
     "Pass FP arguments in FP registers" },		\
  {"no-apcs-float",	       -ARM_FLAG_APCS_FLOAT, "" }, \
  {"apcs-reentrant",		ARM_FLAG_APCS_REENT, 	\
     "Generate re-entrant, PIC code" },			\
  {"no-apcs-reentrant",	       -ARM_FLAG_APCS_REENT, "" }, \
  {"short-load-bytes",		ARM_FLAG_SHORT_BYTE, 	\
     "Load shorts a byte at a time" },			\
  {"no-short-load-bytes",      -ARM_FLAG_SHORT_BYTE, "" }, \
  {"short-load-words",	       -ARM_FLAG_SHORT_BYTE, 	\
     "Load words a byte at a time" },			\
  {"no-short-load-words",	ARM_FLAG_SHORT_BYTE, "" }, \
  {"soft-float",		ARM_FLAG_SOFT_FLOAT, 	\
     "Use library calls to perform FP operations" },	\
  {"hard-float",	       -ARM_FLAG_SOFT_FLOAT, 	\
     "Use hardware floating point instructions" },	\
  {"big-endian",		ARM_FLAG_BIG_END, 	\
     "Assume target CPU is configured as big endian" },	\
  {"little-endian",	       -ARM_FLAG_BIG_END, 	\
     "Assume target CPU is configured as little endian" }, \
  {"words-little-endian",       ARM_FLAG_LITTLE_WORDS, 	\
     "Assume big endian bytes, little endian words" },	\
  {"thumb-interwork",		ARM_FLAG_THUMB, 	\
     "Support calls between THUMB and ARM instructions sets" },	\
  {"no-thumb-interwork",       -ARM_FLAG_THUMB, "" },	\
  {"abort-on-noreturn",         ARM_FLAG_ABORT_NORETURN,     \
   "Generate a call to abort if a noreturn function returns"}, \
  {"no-abort-on-noreturn",      -ARM_FLAG_ABORT_NORETURN, ""}, \
  {"sched-prolog",             -ARM_FLAG_NO_SCHED_PRO, 	\
     "Do not move instructions into a function's prologue" }, \
  {"no-sched-prolog",           ARM_FLAG_NO_SCHED_PRO, "" }, \
  SUBTARGET_SWITCHES					\
  {"",				TARGET_DEFAULT }	\
}

#define TARGET_OPTIONS						\
{								\
  {"cpu=",  & arm_select[0].string,				\
     "Specify the name of the target CPU" },			\
  {"arch=", & arm_select[1].string,				\
     "Specify the name of the target architecture" }, 		\
  {"tune=", & arm_select[2].string, "" }, 			\
  {"fpe=",  & target_fp_name, "" }, 				\
  {"fp=",   & target_fp_name,					\
     "Specify the version of the floating point emulator" },	\
  { "structure-size-boundary=", & structure_size_string, 	\
      "Specify the minumum bit alignment of structures" } 	\
}

struct arm_cpu_select
{
  const char *              string;
  const char *              name;
  const struct processors * processors;
};

/* This is a magic array.  If the user specifies a command line switch
   which matches one of the entries in TARGET_OPTIONS then the corresponding
   string pointer will be set to the value specified by the user.  */
extern struct arm_cpu_select arm_select[];

enum prog_mode_type
{
  prog_mode26,
  prog_mode32
};

/* Recast the program mode class to be the prog_mode attribute */
#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)

extern enum prog_mode_type arm_prgmode;

/* What sort of floating point unit do we have? Hardware or software.
   If software, is it issue 2 or issue 3?  */
enum floating_point_type
{
  FP_HARD,
  FP_SOFT2,
  FP_SOFT3
};

/* Recast the floating point class to be the floating point attribute.  */
#define arm_fpu_attr ((enum attr_fpu) arm_fpu)

/* What type of floating point to tune for */
extern enum floating_point_type arm_fpu;

/* What type of floating point instructions are available */
extern enum floating_point_type arm_fpu_arch;

/* Default floating point architecture.  Override in sub-target if
   necessary.  */
#define FP_DEFAULT FP_SOFT2

/* Nonzero if the processor has a fast multiply insn, and one that does
   a 64-bit multiply of two 32-bit values.  */
extern int arm_fast_multiply;

/* Nonzero if this chip supports the ARM Architecture 4 extensions */
extern int arm_arch4;

/* Nonzero if this chip can benefit from load scheduling.  */
extern int arm_ld_sched;

/* Nonzero if this chip is a StrongARM.  */
extern int arm_is_strong;

/* Nonzero if this chip is a an ARM6 or an ARM7.  */
extern int arm_is_6_or_7;

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT  0
#endif

/* The frame pointer register used in gcc has nothing to do with debugging;
   that is controlled by the APCS-FRAME option.  */
/* Not fully implemented yet */
/* #define CAN_DEBUG_WITHOUT_FP 1 */

#define TARGET_MEM_FUNCTIONS 1

#define OVERRIDE_OPTIONS  arm_override_options ()

/* Nonzero if PIC code requires explicit qualifiers to generate
   PLT and GOT relocs rather than the assembler doing so implicitly.
   Subtargets can override this if required.  */
#ifndef NEED_PLT_GOT
#define NEED_PLT_GOT	0
#endif

/* Nonzero if we need to refer to the GOT with a PC-relative
   offset.  In other words, generate

   .word	_GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]  

   rather than

   .word	_GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)

   The default is true, which matches NetBSD.  Subtargets can 
   override this if required.  */
#ifndef GOT_PCREL
#define GOT_PCREL   1
#endif


/* Target machine storage Layout.  */


/* Define this macro if it is advisable to hold scalars in registers
   in a wider mode than that declared by the program.  In such cases,
   the value is constrained to be within the bounds of the declared
   type, but kept valid in the wider mode.  The signedness of the
   extension may differ from that of the type.  */

/* It is far faster to zero extend chars than to sign extend them */

#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
  if (GET_MODE_CLASS (MODE) == MODE_INT		\
      && GET_MODE_SIZE (MODE) < 4)      	\
    {						\
      if (MODE == QImode)			\
	UNSIGNEDP = 1;				\
      else if (MODE == HImode)			\
	UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0;	\
      (MODE) = SImode;				\
    }

/* Define this macro if the promotion described by `PROMOTE_MODE'
   should also be done for outgoing function arguments.  */
/* This is required to ensure that push insns always push a word.  */
#define PROMOTE_FUNCTION_ARGS

/* Define for XFmode extended real floating point support.
   This will automatically cause REAL_ARITHMETIC to be defined.  */
/* For the ARM:
   I think I have added all the code to make this work.  Unfortunately,
   early releases of the floating point emulation code on RISCiX used a
   different format for extended precision numbers.  On my RISCiX box there
   is a bug somewhere which causes the machine to lock up when running enquire
   with long doubles.  There is the additional aspect that Norcroft C
   treats long doubles as doubles and we ought to remain compatible.
   Perhaps someone with an FPA coprocessor and not running RISCiX would like
   to try this someday. */
/* #define LONG_DOUBLE_TYPE_SIZE 96 */

/* Disable XFmode patterns in md file */
#define ENABLE_XF_PATTERNS 0

/* Define if you don't want extended real, but do want to use the
   software floating point emulator for REAL_ARITHMETIC and
   decimal <-> binary conversion. */
/* See comment above */
#define REAL_ARITHMETIC

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.  
   Most ARM processors are run in little endian mode, so that is the default.
   If you want to have it run-time selectable, change the definition in a
   cover file to be TARGET_BIG_ENDIAN.  */
#define BYTES_BIG_ENDIAN  (TARGET_BIG_END != 0)

/* Define this if most significant word of a multiword number is the lowest
   numbered.
   This is always false, even when in big-endian mode.  */
#define WORDS_BIG_ENDIAN  (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)

/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
   on processor pre-defineds when compiling libgcc2.c.  */
#if defined(__ARMEB__) && !defined(__ARMWEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif

/* Define this if most significant word of doubles is the lowest numbered.
   This is always true, even when in little-endian mode.  */
#define FLOAT_WORDS_BIG_ENDIAN 1

/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT  8

#define BITS_PER_WORD  32

#define UNITS_PER_WORD	4

#define POINTER_SIZE  32

#define PARM_BOUNDARY  	32

#define STACK_BOUNDARY  32

#define FUNCTION_BOUNDARY  32

#define EMPTY_FIELD_BOUNDARY  32

#define BIGGEST_ALIGNMENT  32

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  (TREE_CODE (EXP) == STRING_CST        \
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

/* Every structures size must be a multiple of 32 bits.  */
/* This is for compatibility with ARMCC.  ARM SDT Reference Manual
   (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
   boundaries".  */
#ifndef STRUCTURE_SIZE_BOUNDARY
#define STRUCTURE_SIZE_BOUNDARY 32
#endif

/* Used when parsing command line option -mstructure_size_boundary.  */
extern const char * structure_size_string;

/* Non-zero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 1

#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT


/* Standard register usage.  */

/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
   (S - saved over call).

	r0	   *	argument word/integer result
	r1-r3		argument word

	r4-r8	     S	register variable
	r9	     S	(rfp) register variable (real frame pointer)
	
	r10  	   F S	(sl) stack limit (used by -mapcs-stack-check)
	r11 	   F S	(fp) argument pointer
	r12		(ip) temp workspace
	r13  	   F S	(sp) lower end of current stack frame
	r14		(lr) link address/workspace
	r15	   F	(pc) program counter

	f0		floating point result
	f1-f3		floating point scratch

	f4-f7	     S	floating point variable

	cc		This is NOT a real register, but is used internally
	                to represent things that use or set the condition
			codes.
	sfp             This isn't either.  It is used during rtl generation
	                since the offset between the frame pointer and the
			auto's isn't known until after register allocation.
	afp		Nor this, we only need this because of non-local
	                goto.  Without it fp appears to be used and the
			elimination code won't get rid of sfp.  It tracks
			fp exactly at all times.

   *: See CONDITIONAL_REGISTER_USAGE  */

/* The stack backtrace structure is as follows:
  fp points to here:  |  save code pointer  |      [fp]
                      |  return link value  |      [fp, #-4]
                      |  return sp value    |      [fp, #-8]
                      |  return fp value    |      [fp, #-12]
                     [|  saved r10 value    |]
                     [|  saved r9 value     |]
                     [|  saved r8 value     |]
                     [|  saved r7 value     |]
                     [|  saved r6 value     |]
                     [|  saved r5 value     |]
                     [|  saved r4 value     |]
                     [|  saved r3 value     |]
                     [|  saved r2 value     |]
                     [|  saved r1 value     |]
                     [|  saved r0 value     |]
                     [|  saved f7 value     |]     three words
                     [|  saved f6 value     |]     three words
                     [|  saved f5 value     |]     three words
                     [|  saved f4 value     |]     three words
  r0-r3 are not normally saved in a C function.  */

/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP.  */
#define FIRST_PSEUDO_REGISTER  27

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */