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📄 arm.h

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/* Definitions of target machine for GNU compiler, for ARM.   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000   Free Software Foundation, Inc.   Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)   and Martin Simmons (@harleqn.co.uk).   More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)   This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING.  If not, write tothe Free Software Foundation, 59 Temple Place - Suite 330,Boston, MA 02111-1307, USA.  *//* Configuration triples for ARM ports work as follows:   (This is a bit of a mess and needs some thought)   arm-*-*: little endian   armel-*-*: little endian   armeb-*-*: big endian   If a non-embedded environment (ie: "real" OS) is specified, `arm'   should default to that used by the OS.*/#ifndef __ARM_H__#define __ARM_H__#define TARGET_CPU_arm2		0x0000#define TARGET_CPU_arm250	0x0000#define TARGET_CPU_arm3		0x0000#define TARGET_CPU_arm6		0x0001#define TARGET_CPU_arm600	0x0001#define TARGET_CPU_arm610	0x0002#define TARGET_CPU_arm7		0x0001#define TARGET_CPU_arm7m	0x0004#define TARGET_CPU_arm7dm	0x0004#define TARGET_CPU_arm7dmi	0x0004#define TARGET_CPU_arm700	0x0001#define TARGET_CPU_arm710	0x0002#define TARGET_CPU_arm7100	0x0002#define TARGET_CPU_arm7500	0x0002#define TARGET_CPU_arm7500fe	0x1001#define TARGET_CPU_arm7tdmi	0x0008#define TARGET_CPU_arm8		0x0010#define TARGET_CPU_arm810	0x0020#define TARGET_CPU_strongarm	0x0040#define TARGET_CPU_strongarm110 0x0040#define TARGET_CPU_strongarm1100 0x0040#define TARGET_CPU_arm9		0x0080#define TARGET_CPU_arm9tdmi	0x0080/* Configure didn't specify */#define TARGET_CPU_generic	0x8000enum arm_cond_code{  ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,  ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV};extern enum arm_cond_code arm_current_cc;extern char *arm_condition_codes[];#define ARM_INVERSE_CONDITION_CODE(X)  ((enum arm_cond_code) (((int)X) ^ 1))/* This is needed by the tail-calling peepholes */extern int frame_pointer_needed;/* Just in case configure has failed to define anything. */#ifndef TARGET_CPU_DEFAULT#define TARGET_CPU_DEFAULT TARGET_CPU_generic#endif/* If the configuration file doesn't specify the cpu, the subtarget may   override it.  If it doesn't, then default to an ARM6. */#if TARGET_CPU_DEFAULT == TARGET_CPU_generic#undef TARGET_CPU_DEFAULT#ifdef SUBTARGET_CPU_DEFAULT#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT#else#define TARGET_CPU_DEFAULT TARGET_CPU_arm6#endif#endif#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"#else#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"#else#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"#else#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"#else#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"#elseUnrecognized value in TARGET_CPU_DEFAULT.#endif#endif#endif#endif#endif#ifndef CPP_PREDEFINES#define CPP_PREDEFINES  "-Darm -Acpu(arm) -Amachine(arm)"#endif#define CPP_SPEC "\%(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \%(cpp_endian) %(subtarget_cpp_spec)"/* Set the architecture define -- if -march= is set, then it overrides   the -mcpu= setting.  */#define CPP_CPU_ARCH_SPEC "\%{march=arm2:-D__ARM_ARCH_2__} \%{march=arm250:-D__ARM_ARCH_2__} \%{march=arm3:-D__ARM_ARCH_2__} \%{march=arm6:-D__ARM_ARCH_3__} \%{march=arm600:-D__ARM_ARCH_3__} \%{march=arm610:-D__ARM_ARCH_3__} \%{march=arm7:-D__ARM_ARCH_3__} \%{march=arm700:-D__ARM_ARCH_3__} \%{march=arm710:-D__ARM_ARCH_3__} \%{march=arm7100:-D__ARM_ARCH_3__} \%{march=arm7500:-D__ARM_ARCH_3__} \%{march=arm7500fe:-D__ARM_ARCH_3__} \%{march=arm7m:-D__ARM_ARCH_3M__} \%{march=arm7dm:-D__ARM_ARCH_3M__} \%{march=arm7dmi:-D__ARM_ARCH_3M__} \%{march=arm7tdmi:-D__ARM_ARCH_4T__} \%{march=arm8:-D__ARM_ARCH_4__} \%{march=arm810:-D__ARM_ARCH_4__} \%{march=arm9:-D__ARM_ARCH_4T__} \%{march=arm9tdmi:-D__ARM_ARCH_4T__} \%{march=strongarm:-D__ARM_ARCH_4__} \%{march=strongarm110:-D__ARM_ARCH_4__} \%{march=strongarm1100:-D__ARM_ARCH_4__} \%{march=armv2:-D__ARM_ARCH_2__} \%{march=armv2a:-D__ARM_ARCH_2__} \%{march=armv3:-D__ARM_ARCH_3__} \%{march=armv3m:-D__ARM_ARCH_3M__} \%{march=armv4:-D__ARM_ARCH_4__} \%{march=armv4t:-D__ARM_ARCH_4T__} \%{!march=*: \ %{mcpu=arm2:-D__ARM_ARCH_2__} \ %{mcpu=arm250:-D__ARM_ARCH_2__} \ %{mcpu=arm3:-D__ARM_ARCH_2__} \ %{mcpu=arm6:-D__ARM_ARCH_3__} \ %{mcpu=arm600:-D__ARM_ARCH_3__} \ %{mcpu=arm610:-D__ARM_ARCH_3__} \ %{mcpu=arm7:-D__ARM_ARCH_3__} \ %{mcpu=arm700:-D__ARM_ARCH_3__} \ %{mcpu=arm710:-D__ARM_ARCH_3__} \ %{mcpu=arm7100:-D__ARM_ARCH_3__} \ %{mcpu=arm7500:-D__ARM_ARCH_3__} \ %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ %{mcpu=arm8:-D__ARM_ARCH_4__} \ %{mcpu=arm810:-D__ARM_ARCH_4__} \ %{mcpu=arm9:-D__ARM_ARCH_4T__} \ %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ %{mcpu=strongarm:-D__ARM_ARCH_4__} \ %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ %{!mcpu*:%(cpp_cpu_arch_default)}} \"/* Define __APCS_26__ if the PC also contains the PSR */#define CPP_APCS_PC_SPEC "\%{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ -D__APCS_32__} \%{mapcs-26:-D__APCS_26__} \%{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \"#ifndef CPP_APCS_PC_DEFAULT_SPEC#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"#endif#define CPP_FLOAT_SPEC "\%{msoft-float:\  %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \  -D__SOFTFP__} \%{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \"/* Default is hard float, which doesn't define anything */#define CPP_FLOAT_DEFAULT_SPEC ""#define CPP_ENDIAN_SPEC "\%{mbig-endian: \  %{mlittle-endian: \    %e-mbig-endian and -mlittle-endian may not be used together} \  -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \%{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \"/* Default is little endian, which doesn't define anything. */#define CPP_ENDIAN_DEFAULT_SPEC ""#define CC1_SPEC ""/* This macro defines names of additional specifications to put in the specs   that can be used in various specifications like CC1_SPEC.  Its definition   is an initializer with a subgrouping for each command option.   Each subgrouping contains a string constant, that defines the   specification name, and a string constant that used by the GNU CC driver   program.   Do not define this macro if it does not need to do anything.  */#define EXTRA_SPECS						\  { "cpp_cpu_arch",		CPP_CPU_ARCH_SPEC },		\  { "cpp_cpu_arch_default",	CPP_ARCH_DEFAULT_SPEC },	\  { "cpp_apcs_pc",		CPP_APCS_PC_SPEC },		\  { "cpp_apcs_pc_default",	CPP_APCS_PC_DEFAULT_SPEC },	\  { "cpp_float",		CPP_FLOAT_SPEC },		\  { "cpp_float_default",	CPP_FLOAT_DEFAULT_SPEC },	\  { "cpp_endian",		CPP_ENDIAN_SPEC },		\  { "cpp_endian_default",	CPP_ENDIAN_DEFAULT_SPEC },	\  { "subtarget_cpp_spec",	SUBTARGET_CPP_SPEC },           \  SUBTARGET_EXTRA_SPECS#define SUBTARGET_EXTRA_SPECS#define SUBTARGET_CPP_SPEC      ""/* Run-time Target Specification.  */#ifndef TARGET_VERSION#define TARGET_VERSION  \  fputs (" (ARM/generic)", stderr);#endif/* Run-time compilation parameters selecting different hardware subsets.  */extern int target_flags;/* The floating point instruction architecture, can be 2 or 3 */extern const char * target_fp_name;/* Nonzero if the function prologue (and epilogue) should obey   the ARM Procedure Call Standard.  */#define ARM_FLAG_APCS_FRAME	(0x0001)/* Nonzero if the function prologue should output the function name to enable   the post mortem debugger to print a backtrace (very useful on RISCOS,   unused on RISCiX).  Specifying this flag also enables   -fno-omit-frame-pointer.   XXX Must still be implemented in the prologue.  */#define ARM_FLAG_POKE         (0x0002)/* Nonzero if floating point instructions are emulated by the FPE, in which   case instruction scheduling becomes very uninteresting.  */#define ARM_FLAG_FPE          (0x0004)/* Nonzero if destined for a processor in 32-bit program mode.  Takes out bit   that assume restoration of the condition flags when returning from a   branch and link (ie a function).  */#define ARM_FLAG_APCS_32      (0x0020)/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection).  *//* Nonzero if stack checking should be performed on entry to each function   which allocates temporary variables on the stack.  */#define ARM_FLAG_APCS_STACK   (0x0040)/* Nonzero if floating point parameters should be passed to functions in   floating point registers.  */#define ARM_FLAG_APCS_FLOAT   (0x0080)/* Nonzero if re-entrant, position independent code should be generated.   This is equivalent to -fpic.  */#define ARM_FLAG_APCS_REENT   (0x0100)/* Nonzero if the MMU will trap unaligned word accesses, so shorts must be   loaded byte-at-a-time.  */#define ARM_FLAG_SHORT_BYTE   (0x0200)/* Nonzero if all floating point instructions are missing (and there is no   emulator either).  Generate function calls for all ops in this case.  */#define ARM_FLAG_SOFT_FLOAT   (0x0400)/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1.  */#define ARM_FLAG_BIG_END      (0x0800)/* Nonzero if we should compile for Thumb interworking.  */#define ARM_FLAG_THUMB          (0x1000)/* Nonzero if we should have little-endian words even when compiling for   big-endian (for backwards compatibility with older versions of GCC).  */#define ARM_FLAG_LITTLE_WORDS	(0x2000)/* Nonzero if we need to protect the prolog from scheduling */#define ARM_FLAG_NO_SCHED_PRO	(0x4000)/* Nonzero if a call to abort should be generated if a noreturn function tries to return. */#define ARM_FLAG_ABORT_NORETURN (0x8000)#define TARGET_APCS			(target_flags & ARM_FLAG_APCS_FRAME)#define TARGET_POKE_FUNCTION_NAME	(target_flags & ARM_FLAG_POKE)#define TARGET_FPE			(target_flags & ARM_FLAG_FPE)#define TARGET_APCS_32			(target_flags & ARM_FLAG_APCS_32)#define TARGET_APCS_STACK		(target_flags & ARM_FLAG_APCS_STACK)#define TARGET_APCS_FLOAT		(target_flags & ARM_FLAG_APCS_FLOAT)#define TARGET_APCS_REENT		(target_flags & ARM_FLAG_APCS_REENT)/* Note: TARGET_SHORT_BY_BYTES is really a misnomer.  What it means is   that short values sould not be accessed using word load instructions   as there is a possibility that they may not be word aligned and this   would generate an MMU fault.  On processors which do not have a 16 bit   load instruction therefore, short values must be loaded by individual   byte accesses rather than loading a word and then shifting the desired   value into place.  */#define TARGET_SHORT_BY_BYTES		(target_flags & ARM_FLAG_SHORT_BYTE)#define TARGET_SOFT_FLOAT		(target_flags & ARM_FLAG_SOFT_FLOAT)#define TARGET_HARD_FLOAT		(! TARGET_SOFT_FLOAT)#define TARGET_BIG_END			(target_flags & ARM_FLAG_BIG_END)#define TARGET_THUMB_INTERWORK		(target_flags & ARM_FLAG_THUMB)#define TARGET_LITTLE_WORDS		(target_flags & ARM_FLAG_LITTLE_WORDS)#define TARGET_NO_SCHED_PRO		(target_flags & ARM_FLAG_NO_SCHED_PRO)#define TARGET_ABORT_NORETURN           (target_flags & ARM_FLAG_ABORT_NORETURN)/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.   Bit 31 is reserved.  See riscix.h.  */#ifndef SUBTARGET_SWITCHES#define SUBTARGET_SWITCHES#endif#define TARGET_SWITCHES  				\

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