gmicro.md

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  "*
{
  if (GET_CODE (operands[1]) == CONST_INT)
    return \"and %1,%0.w\";
  return \"and %1.h,%0.w\";
}")


(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))
		(match_operand:SI 2 "general_operand" "0")))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == CONST_INT)
    return \"and %1,%0.w\";
  return \"and %1.b,%0.w\";
}")

;; inclusive-or instructions

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(ior:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "*
{
  register int logval;
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) >> 16 == 0
      && (GREG_P (operands[0])
	  || offsettable_memref_p (operands[0])))
    { 
      if (GET_CODE (operands[0]) != REG)
        operands[0] = adj_offsettable_operand (operands[0], 2);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      return \"or.h %2,%0\";
    }
  if (GET_CODE (operands[2]) == CONST_INT
      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
      && (GREG_P (operands[0])
	  || offsettable_memref_p (operands[0])))
    { 
      if (GREG_P (operands[0]))
	{
	  if (logval < 7)
	    {
	      operands[1] = GEN_INT (7 - logval);
	      return \"bset.b %1,%0\";
	    }
	  operands[1] = GEN_INT (31 - logval);
	  return \"bset.w %1,%0\";
	}
      else
        {
	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
	  operands[1] = GEN_INT (7 - (logval % 8));
	}
      return \"bset.b %1,%0\";
    }
  return \"or.w %2,%0\";
}")

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(ior:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "or.h %2,%0")

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(ior:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "or.b %2,%0")

;; xor instructions

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(xor:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) >> 16 == 0
      && (offsettable_memref_p (operands[0]) || GREG_P (operands[0])))
    { 
      if (! GREG_P (operands[0]))
	operands[0] = adj_offsettable_operand (operands[0], 2);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      return \"xor.h %2,%0\";
    }
  return \"xor.w %2,%0\";
}")

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(xor:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "xor.h %2,%0")

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(xor:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "xor.b %2,%0")

;; negation instructions

(define_insn "negsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
  ""
  "neg.w %0")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "neg.h %0")

(define_insn "negqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
  ""
  "neg.b %0")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
  "TARGET_FPU"
  "fneg.s %f1,%0")


(define_insn "negdf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
  "TARGET_FPU"
  "fneg.d %f1,%0")


;; Absolute value instructions

(define_insn "abssf2"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
  "TARGET_FPU"
  "fabs.s %f1,%0")

(define_insn "absdf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
  "TARGET_FPU"
  "fabs.d %f1,%0")


;; one complement instructions

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(not:SI (match_operand:SI 1 "general_operand" "0")))]
  ""
  "not.w %0")

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(not:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "not.h %0")

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(not:QI (match_operand:QI 1 "general_operand" "0")))]
  ""
  "not.b %0")

;; Optimized special case of shifting.
;; Must precede the general case.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
		     (const_int 24)))]
  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
  "mov:l %1.b,%0.w")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
		     (const_int 24)))]
  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
  "movu %1.b,%0.w")

(define_insn ""
  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
		       (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
				    (const_int 24))))]
  "(GET_CODE (operands[0]) == CONST_INT
    && (INTVAL (operands[0]) & ~0xff) == 0)"
  "*
{
  cc_status.flags |= CC_REVERSED;
  if (my_signed_comp (insn))
    return \"cmp.b %0,%1\";
  return \"cmpu.b %0,%1\";
}")

(define_insn ""
  [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
				    (const_int 24))
		       (match_operand:QI 1 "general_operand" "i")))]
  "(GET_CODE (operands[1]) == CONST_INT
    && (INTVAL (operands[1]) & ~0xff) == 0)"
  "*
  if (my_signed_comp (insn))
	return \"cmp.b %1,%0\";
  return \"cmpu.b %1,%0\";
")

(define_insn ""
  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
		       (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
				    (const_int 24))))]
  "(GET_CODE (operands[0]) == CONST_INT
    && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
  "*
  cc_status.flags |= CC_REVERSED;
  if (my_signed_comp (insn))
	return \"cmp.b %0,%1\";
  return \"cmpu.b %0,%1\";
")

(define_insn ""
  [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
				    (const_int 24))
		       (match_operand:QI 1 "general_operand" "i")))]
  "(GET_CODE (operands[1]) == CONST_INT
    && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
  "*
  if (my_signed_comp (insn))
	return \"cmp.b %1,%0\";
  return \"cmpu.b %1,%0\";
")

;; arithmetic shift instructions
;; We don't need the shift memory by 1 bit instruction

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(ashift:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "sha.w %2,%0")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(ashift:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "sha.h %2,%0")

(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(ashift:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "sha.b %2,%0")

;; Arithmetic right shift on the Gmicro works by negating the shift count

;; ashiftrt -> ashift
(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(ashift:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "{ operands[2] = negate_rtx (SImode, operands[2]); }")

;; ashiftrt -> ashift
(define_expand "ashrhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(ashift:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  " { operands[2] = negate_rtx (HImode, operands[2]); }")

;; ashiftrt -> ashift
(define_expand "ashrqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(ashift:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  " { operands[2] = negate_rtx (QImode, operands[2]); }")

;; logical shift instructions

;; Logical right shift on the gmicro works by negating the shift count,
;; then emitting a right shift with the shift count negated.  This means
;; that all actual shift counts in the RTL will be positive.  This 
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
;; which isn't valid.

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
		     (match_operand:SI 2 "general_operand" "g")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "shl.w %n2,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
		     (neg:SI (match_operand:SI 2 "general_operand" "rm"))))]
  ""
  "shl.w %2,%0")

(define_expand "lshrhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
		     (match_operand:HI 2 "general_operand" "g")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "const_int_operand" "n")))]
  ""
  "shl.h %n2,%0")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (neg:HI (match_operand:HI 2 "general_operand" "rm"))))]
  ""
  "shl.h %2,%0")

(define_expand "lshrqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
		     (match_operand:QI 2 "general_operand" "g")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "const_int_operand" "n")))]
  ""
  "shl.b %n2,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
		     (neg:QI (match_operand:QI 2 "general_operand" "rm"))))]
  ""
  "shl.b %2,%0")

;; rotate instructions

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(rotate:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "rol.w %2,%0")

(define_insn "rotlhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(rotate:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "rol.h %2,%0")

(define_insn "rotlqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(rotate:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "rol.b %2,%0")

(define_expand "rotrsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  " { operands[2] = negate_rtx (SImode, operands[2]); }")

(define_expand "rotrhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  " { operands[2] = negate_rtx (HImode, operands[2]); }")

(define_expand "rotrqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  " { operands[2] = negate_rtx (QImode, operands[2]); }")

;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; These handle aligned 8-bit and 16-bit fields,
;; which can usually be done with move instructions.

;; Should I add  mode_dependent_address_p ????

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
			 (match_operand:SI 1 "immediate_operand" "i")
			 (match_operand:SI 2 "immediate_operand" "i"))
	(match_operand:SI 3 "general_operand" "rm"))]
  "TARGET_BITFIELD
   && GET_CODE (operands[1]) == CONST_INT
   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
   && GET_CODE (operands[2]) == CONST_INT
   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
   && (GET_CODE (operands[0]) != REG
       || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))"
  "*
{
  if (GET_CODE (operands[3]) == MEM)
    operands[3] = adj_offsettable_operand (operands[3],
					   (32 - INTVAL (operands[1])) / 8);

  if (GET_CODE (operands[0]) == REG)
    {
      if (INTVAL (operands[1]) == 8)
	return \"movu %3.b,%0.w\";
      return \"movu %3.h,%0.w\";
    }
  else
    {
      operands[0]
	= adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
      if (INTVAL (operands[1]) == 8)
	return \"mov.b %3,%0\";
      return \"mov.h %3,%0\";
    }
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=&r")
	(zero_extract:SI (match_operand:SI 1 "register_operand" "rm")
			 (match_operand:SI 2 "immediate_operand" "i")
			 (match_operand:SI 3 "immediate_operand" "i")))]
  "TARGET_BITFIELD
   && GET_CODE (operands[2]) == CONST_INT
   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
   && GET_CODE (operands[3]) == CONST_INT
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
  "*
{
  if (!REG_P (operands[1]))
    operands[1]
      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);

  if (REG_P (operands[0]))
    {
      if (REG_P (operands[1]))
	{
	  if (INTVAL (operands[2]) == 8)
	    {			/* width == 8 */
	      switch (INTVAL (operands[3]))
		{
		case 0:
		  return \"mov.w %1,%0;shl.w #-24,%0\";
		  break;
		case 8:
		  return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\";
		  break;
		case 16:
		  return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\";
		  break;
		case 24:
		  return \"movu %1.b,%0.w\";
		  break;
		default:
		  myabort (2);
		}
	    }
	  else
	    {