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	(float:SF (match_operand:QI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.b,%0.s")

(define_insn "floatqidf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(float:DF (match_operand:QI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.b,%0.d")

;;; Convert a float to a float whose value is an integer.
;;; This is the first stage of converting it to an integer type.
;
;(define_insn "ftruncdf2"
;  [(set (match_operand:DF 0 "general_operand" "=f")
;	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
;  "TARGET_FPU"
;  "*
;{
;  return \"fintrz.d %f1,%0\";
;}")
;
;(define_insn "ftruncsf2"
;  [(set (match_operand:SF 0 "general_operand" "=f")
;	(fix:SF (match_operand:SF 1 "general_operand" "fFm")))]
;  "TARGET_FPU"
;  "*
;{
;  return \"fintrz.s %f1,%0\";
;}")

;; Convert a float to an integer.

(define_insn "fix_truncsfqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.s,%0.b")

(define_insn "fix_truncsfhi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.s,%0.h")

(define_insn "fix_truncsfsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.s,%0.w")

(define_insn "fix_truncdfqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.d,%0.b")

(define_insn "fix_truncdfhi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.d,%0.h")

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
  "TARGET_FPU"
  "fsti %1.d,%0.w")


;;; Special add patterns
;;; 89.09.28

;; This should be redundant; please find out why regular addsi3
;; fails to match this case.

;(define_insn ""
;  [(set (mem:SI (plus:SI
;		    (plus:SI (match_operand 0 "general_operand" "r")
;			     (match_operand 1 "general_operand" "r"))
;		    (match_operand 2 "general_operand" "i")))
;	(plus:SI
;	    (mem:SI (plus:SI
;			(plus:SI (match_dup 0)
;				 (match_dup 1))
;			(match_dup 2)))
;	    (match_operand 3 "general_operand" "rmi")))]
;  ""
;  "add.w %3,@(%c2,%0,%1)")


;; add instructions

;; Note that the last two alternatives are near-duplicates
;; in order to handle insns generated by reload.
;; This is needed since they are not themselves reloaded,
;; so commutativity won't apply to them.

(define_insn "addsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r")
	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri")
		 (match_operand:SI 2 "general_operand" "rmi,ri,r")))]
  ""
  "*
{
  if (which_alternative == 0)
    {
      if (GET_CODE (operands[2]) == CONST_INT)
	{
	  operands[1] = operands[2];
	  return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
	}
      else
	return \"add.w %2,%0\";
    }
  else
    {
      if (GET_CODE (operands[1]) == REG
	  && REGNO (operands[0]) == REGNO (operands[1]))
	return \"add.w %2,%0\";
      if (GET_CODE (operands[2]) == REG
	  && REGNO (operands[0]) == REGNO (operands[2]))
	return \"add.w %1,%0\";

      if (GET_CODE (operands[1]) == REG)
	{
	  if (GET_CODE (operands[2]) == REG)
	    return \"mova.w @(%1,%2),%0\";
	  else
	    return \"mova.w @(%c2,%1),%0\";
	}
      else
	return \"mova.w @(%c1,%2),%0\";
    }
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(plus:SI (match_operand:SI 1 "general_operand" "0")
		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
  ""
  "*
{
  if (CONSTANT_P (operands[2]))
    {
      operands[1] = operands[2];
      return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
    }
  else
    return \"add %2.h,%0.w\";
}")

(define_insn "addhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(plus:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) < 0)
    return \"sub.h #%n2,%0\";
  if (GREG_P (operands[0]))
    {
      if (CONSTANT_P (operands[2]))
	return \"add:l %2,%0.w\";
      else
	return \"add:l %2.h,%0.w\";
    }
  return \"add.h %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
	(plus:HI (match_dup 0)
		 (match_operand:HI 1 "general_operand" "rmi")))]
  ""
  "add.h %1,%0")

(define_insn "addqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(plus:QI (match_operand:QI 1 "general_operand" "%0")
		 (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) < 0)
    return \"sub.b #%n2,%0\";
  if (GREG_P (operands[0]))
    {
      if (CONSTANT_P (operands[2]))
	return \"add:l %2,%0.w\";
      else
	return \"add:l %2.b,%0.w\";
    }
  return \"add.b %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
	(plus:QI (match_dup 0)
		 (match_operand:QI 1 "general_operand" "rmi")))]
  ""
  "add.b %1,%0")

(define_insn "adddf3"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(plus:DF (match_operand:DF 1 "general_operand" "%0")
		 (match_operand:DF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fadd.d %f2,%0")

(define_insn "addsf3"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(plus:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fadd.s %f2,%0")

;; subtract instructions

(define_insn "subsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm,!r")
	(minus:SI (match_operand:SI 1 "general_operand" "0,r")
		  (match_operand:SI 2 "general_operand" "rmi,i")))]
  ""
  "*
{
  if (which_alternative == 0
      || (GET_CODE (operands[1]) == REG
	  && REGNO (operands[0]) == REGNO (operands[1])))
    {
      if (GET_CODE (operands[2]) == CONST_INT)
	{
	  operands[1] = operands[2];
	  return sub_imm_word (INTVAL (operands[1]),
			       operands[0], &operands[1]);
	}
      else
	return \"sub.w %2,%0\";
    }
  else
    return \"mova.w @(%n2,%1),%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(minus:SI (match_operand:SI 1 "general_operand" "0")
		  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
  ""
  "sub %2.h,%0.w")

(define_insn "subhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(minus:HI (match_operand:HI 1 "general_operand" "0")
		  (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) < 0
      && INTVAL (operands[2]) != 0x8000)
    return \"add.h #%n2,%0\";
  return \"sub.h %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
	(minus:HI (match_dup 0)
		  (match_operand:HI 1 "general_operand" "rmi")))]
  ""
  "sub.h %1,%0")

(define_insn "subqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(minus:QI (match_operand:QI 1 "general_operand" "0")
		  (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) < 0
      && INTVAL (operands[2]) != 0x80)
    return \"add.b #%n2,%0\";
  return \"sub.b %2,%0\";
}")

(define_insn ""
  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
	(minus:QI (match_dup 0)
		  (match_operand:QI 1 "general_operand" "rmi")))]
  ""
  "sub.b %1,%0")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(minus:DF (match_operand:DF 1 "general_operand" "0")
		  (match_operand:DF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fsub.d %f2,%0")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(minus:SF (match_operand:SF 1 "general_operand" "0")
		  (match_operand:SF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fsub.s %f2,%0")


;; multiply instructions

(define_insn "mulqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(mult:QI (match_operand:QI 1 "general_operand" "%0")
		 (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "mul.b %2,%0")


(define_insn "mulhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(mult:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "mul.h %2,%0")

;; define_insn "mulhisi3"

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(mult:SI (match_operand:SI 1 "general_operand" "%0")
		 (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "mul.w %2,%0")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(mult:DF (match_operand:DF 1 "general_operand" "%0")
		 (match_operand:DF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fmul.d %f2,%0")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(mult:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fmul.s %f2,%0")


;; divide instructions

(define_insn "divqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(div:QI (match_operand:QI 1 "general_operand" "0")
		(match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "div.b %2,%0")

(define_insn "divhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(div:HI (match_operand:HI 1 "general_operand" "0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "div.h %2,%0")

(define_insn "divhisi3"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(div:HI (match_operand:SI 1 "general_operand" "0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "div %2.h,%0.w")

(define_insn "divsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(div:SI (match_operand:SI 1 "general_operand" "0")
		(match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "div.w %2,%0")

(define_insn "udivqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(udiv:QI (match_operand:QI 1 "general_operand" "0")
		 (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "divu.b %2,%0")

(define_insn "udivhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(udiv:HI (match_operand:HI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "divu.h %2,%0")

(define_insn "udivhisi3"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(udiv:HI (match_operand:SI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "divu %2.h,%0.w")

(define_insn "udivsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(udiv:SI (match_operand:SI 1 "general_operand" "0")
		 (match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "divu.w %2,%0")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(div:DF (match_operand:DF 1 "general_operand" "0")
		(match_operand:DF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fdiv.d %f2,%0")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(div:SF (match_operand:SF 1 "general_operand" "0")
		(match_operand:SF 2 "general_operand" "fmG")))]
  "TARGET_FPU"
  "fdiv.s %f2,%0")

;; Remainder instructions.

(define_insn "modqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(mod:QI (match_operand:QI 1 "general_operand" "0")
		(match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "rem.b %2,%0")

(define_insn "modhisi3"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(mod:HI (match_operand:SI 1 "general_operand" "0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "rem.h %2,%0")

(define_insn "umodqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(umod:QI (match_operand:QI 1 "general_operand" "0")
		 (match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "remu.b %2,%0")

(define_insn "umodhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(umod:HI (match_operand:HI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "remu.h %2,%0")

(define_insn "umodhisi3"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(umod:HI (match_operand:SI 1 "general_operand" "0")
		 (match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "remu %2.h,%0.w")

;; define_insn "divmodsi4"

(define_insn "udivmodsi4"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(udiv:SI (match_operand:SI 1 "general_operand" "0")
		 (match_operand:SI 2 "general_operand" "rmi")))
   (set (match_operand:SI 3 "general_operand" "=r")
	(umod:SI (match_dup 1) (match_dup 2)))]
  ""
  "mov.w #0,%3;divx.w %2,%0,%3")

;; logical-and instructions

(define_insn "andsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(and:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "rmi")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
      && (GREG_P (operands[0])
	  || offsettable_memref_p (operands[0])))
   
    { 
      if (GET_CODE (operands[0]) != REG)
        operands[0] = adj_offsettable_operand (operands[0], 2);
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      return \"and.h %2,%0\";
    }
  return \"and.w %2,%0\";
}")

(define_insn "andhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(and:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "rmi")))]
  ""
  "and.h %2,%0")

(define_insn "andqi3"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(and:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "rmi")))]
  ""
  "and.b %2,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))
		(match_operand:SI 2 "general_operand" "0")))]
  ""