gmicro.md

gcc编译工具没有什么特别

  "*
{
  if (GREG_P (operands[0]))
    {
      if (CONSTANT_P (operands[1]))
	return \"mov:l %1,%0.w\";
      else
	return \"mov:l %1.b,%0.w\";
    }
  if (GREG_P (operands[1]))
    return \"mov:s %1.w,%0.b\";
  return \"mov.b %1,%0\";
}")

(define_insn "movstrictqi"
  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
	(match_operand:QI 1 "general_operand" "rmi"))]
  ""
  "mov.b %1,%0")


(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr")
	(match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_single (operands);
      return \"fmov.s %1,%0\";
    case 1:
      return \"fmov.s %1,%0\";
    case 2:
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_single (operands);
      return \"mov.w %1,%0\";
    case 3:
      if (FPU_REG_P (operands[0]))
	return \"mov.w %1,%-\\n\\tfmov.s %+,%0\";
      return \"fmov.s %1,%-\\n\\tmov.w %+,%0\";
    }
}")

(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr")
	(match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_double (operands);
      return \"fmov.d %1,%0\";
    case 1:
      return \"fmov.d %1,%0\";
    case 2:
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_double (operands);
      return output_move_double (operands);
    case 3:
      if (FPU_REG_P (operands[0]))
	{
	  rtx xoperands[2];
	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
	  output_asm_insn (\"mov.w %1,%-\", xoperands);
	  output_asm_insn (\"mov.w %1,%-\", operands);
	  return \"fmov.d %+,%0\";
	}
      else
	{
	  output_asm_insn (\"fmov.d %f1,%-\", operands);
	  output_asm_insn (\"mov.w %+,%0\", operands);
	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
	  return \"mov.w %+,%0\";
	}
    }
}")


;; movdi can apply to fp regs in some cases
;; Must check again.  you can use fsti/fldi, etc.
;; FPU reg should be included ??
;; 89.12.13 for test

(define_insn "movdi"
  ;; Let's see if it really still needs to handle fp regs, and, if so, why.
  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro")
	(match_operand:DI 1 "general_operand" "rF,m,roiF"))]
  ""
  "*
{
  if (FPU_REG_P (operands[0]))
    {
      if (FPU_REG_P (operands[1]))
	return \"fmov.d %1,%0\";
      if (REG_P (operands[1]))
	{
	  rtx xoperands[2];
	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
	  output_asm_insn (\"mov.w %1,%-\", xoperands);
	  output_asm_insn (\"mov.w %1,%-\", operands);
	  return \"fmov.d %+,%0\";
	}
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_double (operands);
      return \"fmov.d %f1,%0\";
    }
  else if (FPU_REG_P (operands[1]))
    {
      if (REG_P (operands[0]))
	{
	  output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands);
	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
	  return \"mov.w %+,%0\";
	}
      else
        return \"fmov.d %f1,%0\";
    }
  return output_move_double (operands);
}
")


;; The definition of this insn does not really explain what it does,
;; but it should suffice
;; that anything generated as this insn will be recognized as one
;; and that it won't successfully combine with anything.

;; This is dangerous when %0 and %1 overlapped !!!!!
;; Ugly code...

(define_insn "movstrhi"
  [(set (match_operand:BLK 0 "general_operand" "=m")
	(match_operand:BLK 1 "general_operand" "m"))
   (use (match_operand:HI 2 "general_operand" "rmi"))
   (clobber (reg:SI 0))
   (clobber (reg:SI 1))
   (clobber (reg:SI 2))]
  ""
  "*
{
  int op2const;
  rtx tmpx;

  if (CONSTANT_P (operands[1]))
    {
      fprintf (stderr, \"smov 1 const err \");
      abort ();
    }
  else if (GET_CODE (operands[1]) == REG)
    {
      fprintf (stderr, \"smov 1 reg err \");
      abort ();
    }
  else if (GET_CODE (operands[1]) == MEM)
    {
      tmpx = XEXP (operands[1], 0);
      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
	{
	  operands[1] = tmpx;
	  output_asm_insn (\"mov.w %1,r0\", operands);
	}
      else
	{
	  output_asm_insn (\"mova %1,r0\", operands);
	}
    }
  else
    {
      fprintf (stderr, \"smov 1 else err \");
      abort ();
      output_asm_insn (\"mova.w %p1,r0\", operands);
    }
    
  if (CONSTANT_P (operands[0]))
    {
      fprintf (stderr, \"smov 0 const err \");
      abort ();
    }
  else if (GET_CODE (operands[0]) == REG)
    {
      fprintf (stderr, \"smov 0 reg err \");
      abort ();
    }
  else if (GET_CODE (operands[0]) == MEM)
    {
      tmpx = XEXP (operands[0], 0);
      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
	{
	  operands[0] = tmpx;
	  output_asm_insn (\"mov.w %0,r1\", operands);
	}
      else
	{
	  output_asm_insn (\"mova %0,r1\", operands);
	}
    }
  else
    {
      fprintf (stderr, \"smov 0 else err \");
      abort ();
    }
    
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      op2const = INTVAL (operands[2]);
      if (op2const % 4 != 0)
	{
	  output_asm_insn (\"mov.w %2,r2\", operands);
	  return \"smov/n/f.b\";
	}
      op2const = op2const / 4;
      if (op2const <= 4)
	{
	  if (op2const == 0)
	    abort (0);
	  if (op2const == 1)
	    return \"mov.w @r0,@r1\";
	  output_asm_insn (\"mov.w @r0,@r1\", operands);
	  if (op2const == 2)
	    return \"mov.w @(4,r0),@(4,r1)\";
	  output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands);
	  if (op2const == 3)
	    return \"mov.w @(8,r0),@(8,r1)\";
	  output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands);
	  return \"mov.w @(12,r0),@(12,r1)\";
	}
	    
      operands[2] = GEN_INT (op2const);
      output_asm_insn (\"mov.w %2,r2\", operands);
      return \"smov/n/f.w\";
    }
  else
    {
      fprintf (stderr, \"smov 0 else err \");
      abort ();
      output_asm_insn (\"mov %2.h,r2.w\", operands);
      return \"smov/n/f.b\";
    }

}")

;; M.Yuhara 89.08.24
;; experiment on the built-in strcpy (__builtin_smov)
;;
;; len = 0 means unknown string length.
;;
;; mem:SI is dummy. Necessary so as not to be deleted by optimization.
;; Use of BLKmode would be better...
;;
;;
(define_insn "smovsi"
  [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm"))
	(mem:SI (match_operand:SI 1 "general_operand" "rm")))
   (use (match_operand:SI 2 "general_operand" "i"))
   (clobber (reg:SI 0))
   (clobber (reg:SI 1))
   (clobber (reg:SI 2))
   (clobber (reg:SI 3))]
  ""
  "*
{
  int len, wlen, blen, offset;
  char tmpstr[128];
  rtx xoperands[1];

  len = INTVAL (operands[2]);
  output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands);
  output_asm_insn (\"mov.w %0,r1\", operands);

  if (len == 0)
    {
      output_asm_insn (\"mov:z.w #0,r2\", operands);
      output_asm_insn (\"mov:z.w #0,r3\", operands);
      return \"smov/eq/f.b\\t; end built-in strcpy\";
    }

  wlen = len / 4;
  blen = len - wlen * 4;

  if (wlen > 0)
    {
      if (len <= 40 && !TARGET_FORCE_SMOV)
	{
	  output_asm_insn (\"mov.w @r0,@r1\", operands);
	  offset = 4;
	  while ( (blen = len - offset) > 0)
	    {
	      if (blen >= 4)
		{
		  sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\",
			   offset, offset);
		  output_asm_insn (tmpstr, operands);
		  offset += 4;
		}
	      else if (blen >= 2)
		{
		  sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\",
			   offset, offset);
		  output_asm_insn (tmpstr, operands);
		  offset += 2;
		}
	      else
		{
		  sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\",
			   offset, offset);
		  output_asm_insn (tmpstr, operands);
		  offset++;
		}
	    }
	  return \"\\t\\t; end built-in strcpy\";
	}
      else
	{
	  xoperands[0] = GEN_INT (wlen);
	  output_asm_insn (\"mov.w %0,r2\", xoperands);
	  output_asm_insn (\"smov/n/f.w\", operands);
	}
    }

  if (blen >= 2)
    {
      output_asm_insn (\"mov.h @r0,@r1\", operands);
      if (blen == 3)
	output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands);
    }
  else if (blen == 1)
    {
      output_asm_insn (\"mov.b @r0,@r1\", operands);
    }

  return \"\\t\\t; end built-in strcpy\";
}")

;; truncation instructions
(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(truncate:QI
	 (match_operand:SI 1 "general_operand" "rmi")))]
  ""
  "mov %1.w,%0.b")
;  "*
;{
;  if (GET_CODE (operands[0]) == REG)
;    return \"mov.w %1,%0\";
;  if (GET_CODE (operands[1]) == MEM)
;    operands[1] = adj_offsettable_operand (operands[1], 3);
;  return \"mov.b %1,%0\";
;}")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "general_operand" "=rm")
	(truncate:QI
	 (match_operand:HI 1 "general_operand" "rmi")))]
  ""
  "mov %1.h,%0.b")
;  "*
;{
;  if (GET_CODE (operands[0]) == REG)
;    return \"mov.h %1,%0\";
;  if (GET_CODE (operands[1]) == MEM)
;    operands[1] = adj_offsettable_operand (operands[1], 1);
;  return \"mov.b %1,%0\";
;}")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(truncate:HI
	 (match_operand:SI 1 "general_operand" "rmi")))]
  ""
  "mov %1.w,%0.h")
;  "*
;{
;  if (GET_CODE (operands[0]) == REG)
;    return \"mov.w %1,%0\";
;  if (GET_CODE (operands[1]) == MEM)
;    operands[1] = adj_offsettable_operand (operands[1], 2);
;  return \"mov.h %1,%0\";
;}")

;; zero extension instructions
;; define_expand (68k) -> define_insn (Gmicro)

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
  ""
  "movu %1.h,%0.w")


(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "movu %1.b,%0.h")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "movu %1.b,%0.w")


;; sign extension instructions

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
  ""
  "mov %1.h,%0.w")


(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "mov %1.b,%0.h")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "mov %1.b,%0.w")



;; Conversions between float and double.

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "general_operand" "=*frm,f")
	(float_extend:DF
	  (match_operand:SF 1 "general_operand" "f,rmF")))]
  "TARGET_FPU"
  "*
{
  if (FPU_REG_P (operands[0]))
    {
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_move_const_double (operands);
      if (GREG_P (operands[1]))
	{
	  output_asm_insn (\"mov.w %1,%-\", operands);
	  return \"fmov %+.s,%0.d\";
	}
      return \"fmov %1.s,%0.d\";
    }
  else
    {
      if (GREG_P (operands[0]))
	{
	  output_asm_insn (\"fmov %1.s,%-.d\", operands);
	  output_asm_insn (\"mov.w %+,%0\", operands);
	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
	  return \"mov.w %+,%0\";
	}
      return \"fmov %1.s,%0.d\";
    }
}")


(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "general_operand" "=rfm")
	(float_truncate:SF
	  (match_operand:DF 1 "general_operand" "f")))]
  "TARGET_FPU"
  "*
{
  if (GREG_P (operands[0]))
    {
      output_asm_insn (\"fmov %1.d,%-.s\", operands);
      return \"mov.w %+,%0\";
    }
  return \"fmov %1.d,%0.s\";
}")

;; Conversion between fixed point and floating point.
;; Note that among the fix-to-float insns
;; the ones that start with SImode come first.
;; That is so that an operand that is a CONST_INT
;; (and therefore lacks a specific machine mode).
;; will be recognized as SImode (which is always valid)
;; rather than as QImode or HImode.


(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(float:SF (match_operand:SI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.w,%0.s")

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(float:DF (match_operand:SI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.w,%0.d")

(define_insn "floathisf2"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(float:SF (match_operand:HI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.h,%0.s")

(define_insn "floathidf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(float:DF (match_operand:HI 1 "general_operand" "rmi")))]
  "TARGET_FPU"
  "fldi %1.h,%0.d")

(define_insn "floatqisf2"
  [(set (match_operand:SF 0 "general_operand" "=f")