clipper.md

gcc编译工具没有什么特别

 [(set_attr "type" "arith")])

(define_insn "negdf2"
  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
	(neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
  ""
  "negd   %1,%0"
 [(set_attr "type" "fp")])

(define_insn "negsf2"
  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
	(neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
  ""
  "negs   %1,%0"
 [(set_attr "type" "fp")])

(define_insn "negsi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
  ""
  "negw   %1,%0"
 [(set_attr "type" "arith")])


(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
  ""
  "notw   %1,%0"
 [(set_attr "type" "arith")])



;; Right shift on the clipper works by negating the shift count,
;; then emitting a right shift with the shift count negated.  This means
;; that all actual shift counts in the RTL will be positive.

(define_expand "ashrdi3"
  [(set (match_operand:DI 0 "int_reg_operand" "")
	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "shali  $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "shal   %2,%0"
 [(set_attr "type" "arith")])

(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "")
	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "shai   $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "shaw   %2,%0"
 [(set_attr "type" "arith")])

;;
;; left shift
;;

(define_insn "ashldi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
	(ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   shal   %2,%0
   shali  %2,%0"
 [(set_attr "type" "arith")])


(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "*
{
  int val;

  if (which_alternative == 0)
   return \"shaw   %2,%0\";

  val = INTVAL (operands[2]);

  if (val == 2)
    return \"addw   %0,%0\;addw   %0,%0\";

  if (val == 1)
    return \"addw   %0,%0\";

  return \"shai   %2,%0\";
}"
[(set_attr "type" "arith")])

;;
;; logical shift
;;

(define_expand "lshrdi3"
  [(set (match_operand:DI 0 "int_reg_operand" "")
	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "shlli  $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "shll   %2,%0"
 [(set_attr "type" "arith")])

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "")
	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "shli   $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "shlw   %2,%0"
 [(set_attr "type" "arith")])


;;
;; rotate insn
;;
(define_expand "rotrdi3"
  [(set (match_operand:DI 0 "int_reg_operand" "")
	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "rotli  $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:DI 0 "int_reg_operand" "=r")
	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "rotl   %2,%0"
 [(set_attr "type" "arith")])

(define_expand "rotrsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "")
	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
	             (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (match_operand:SI 2 "const_int_operand" "n")))]
  ""
  "roti   $%n2,%0"
 [(set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:SI 0 "int_reg_operand" "=r")
	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
  ""
  "rotw   %2,%0"
 [(set_attr "type" "arith")])

(define_insn "rotldi3"
  [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
	(rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   rotl   %2,%0
   rotli  %2,%0"
 [(set_attr "type" "arith")])

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
	(rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  ""
  "@
   rotw   %2,%0
   roti   %2,%0"
 [(set_attr "type" "arith")])


;;
;; jump and branch insns
;;
(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "b      %l0"
 [(set_attr "type" "branch")])

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "b      (%0)"
 [(set_attr "type" "branch")])

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "breq   %l0"
 [(set_attr "type" "branch")])

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brne   %l0"
 [(set_attr "type" "branch")])

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brgt   %l0"
 [(set_attr "type" "branch")])

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brgtu  %l0"
 [(set_attr "type" "branch")])

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brlt   %l0"
 [(set_attr "type" "branch")])

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brltu  %l0"
 [(set_attr "type" "branch")])

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brge   %l0"
 [(set_attr "type" "branch")])

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "brgeu  %l0"
 [(set_attr "type" "branch")])

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
 ""
 "brle   %l0"
 [(set_attr "type" "branch")])

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
 ""
 "brleu  %l0"
 [(set_attr "type" "branch")])

;; Recognize reversed jumps.
(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
				      [(cc0)
				       (const_int 0)])
		      (pc)
		      (label_ref (match_operand 1 "" ""))))]
 ""
 "br%C0    %l1" ; %C0 negates condition
 [(set_attr "type" "branch")])

;;
;; call instructions
;;
(define_insn "call"
  [(call (match_operand:QI 0 "general_operand" "m")
	 (match_operand:SI 1 "general_operand" ""))]
  ;; Operand 1 not used on the clipper.
  ""
  "call   sp,%0")

(define_insn "call_value"
  [(set (match_operand 0 "" "=rf")
	(call (match_operand:QI 1 "general_operand" "m")
	      (match_operand:SI 2 "general_operand" "g")))]
  ;; Operand 2 not used on the clipper
  ""
  "call   sp,%1")

;; Call subroutine returning any type.

(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
		    (const_int 0))
	      (match_operand 1 "" "")
	      (match_operand 2 "" "")])]
  ""
  "
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());

  DONE;
}")

;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory.  This blocks insns from being moved across this point.

(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] 0)]
  ""
  "")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
  ""
  "b      (%0)"
 [(set_attr "type" "branch")])


(define_insn "nop"
  [(const_int 0)]
  ""
  "noop"
 [(set_attr "type" "arith")
  (set_attr "cc" "unchanged")])



;; while (--foo >= 0)
;;
;; Combiners for 'decrement test and branch' do not work for clipper.
;; These patters are jump_insns that do not allow output reloads and clipper
;; can only decrement and test registers.
;;